On Mon, 15 Jun 2015 20:26:09 -0700 Hal Murray <[email protected]> wrote:
> Does anybody have data on what the "jitter" actually looks like? I'd expect > several blurry peaks, with the spacing between peaks being the step size of > the delay/mux chain and the blur being wider if there is more random logic. Quick googling revieled these two papers: [1] "Jitter issues in clock conditioning with FPGAs", by Aloisio, Giordano, Izzo, 2010 http://dx.doi.org/10.1109/RTC.2010.5750386 [2] "Phase Noise Issues With FPGA-Embedded DLLs and PLLs in HEP Applications", by Aloisio, Giordano, Izzo, 2011 http://dx.doi.org/10.1109/TNS.2011.2143727 Both contain phase noise plots for different configurations of DLLs of Virtex 5. I haven't read them yet, so I cannot say anything about their content. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
