Hi again,
A frequency detector uses a phase-memory one way or another.
Digital FLL detectors recall the sequence of events, see 4046
Phase-Frequency Detector.
Using a phase detector, just differentiate the phase data to get a
frequency difference estimate, however phase-wrapping usually upset the
result. In digital processing avoiding the wrapping upsetting the result
is relatively trivial.
The combined form of phase and frequency detector can take the form of a
+/- 180 degree phase detector range, but as the phase tries to wrap
over, you "lock" to the upper or lower limit to force the integrator to
integrate the frequency compensation in the right direction and
eventually be close enough to hand over to the phase-detector part. This
is for instance what the 4046 detector does, but it has been used elsewhere.
The 4046 has a charge-pump. Hailed by many. Frankly, it's a bad solution
in my mind. The dead-band can be a killer, as I've seen first hand.
There is the 7046 and 9046 naturally.
Doing a phase-detector PI look, a quick FLL type of lock can be achieved
by letting the damping be very high, that is a very high P factor. This
is the AC-path, letting the side-band modulation be high (too high is
however counter-acting) through the Bessel polynomials.
There is so many ways to do this.
In the end, I only consider FLL in context of locking up my PLL fast,
unless I lock to an atomic standard.
Cheers,
Magnus
On 08/29/2015 12:37 AM, Azelio Boriani wrote:
If FLL: something that links frequencies,
PLL: something that links phases,
frequency detector: output proportional to frequency error,
phase detector: output proportional to phase error (XOR),
and the original question (about FLL) was how to implement a simple FLL,
can an FLL be made by a phase detector? Can a PLL be made by a
frequency detector?
Phase_detector_XOR + RC + VCO-> FLL: equal frequencies, phase linked
to VCO odds,
in this case the frequency error is 0.
On Fri, Aug 28, 2015 at 7:14 PM, Charles Steinmetz
<[email protected]> wrote:
Azelio wrote:
OK: the XOR gate with an RC is a defective PLL and a defective FLL. It
is a simple way to have an idea of what an xLL should be but of no
serious use.
No, not at all. I was suggesting that the XOR PLL you were commenting on
had problems.
First, an XOR with or without an RC is not an FLL at all, of any sort.
Second, the XOR gate is a time-honored phase detector for PLLs, and if its
limitations are understood and accounted for, it makes a perfectly
serviceable PD for a PLL. There are other phase detectors that are more
popular these days, for a variety of reasons, but the XOR works just fine in
a proper design.
See, e.g.:
Best, Phase-Locked Loops (2007), pp. 16-18
Gardner, Phaselock Techniques (3rd ed) (2005), pp. 245-46
Wolaver, Phase-Locked Loop Circuit Design (1991) pp. 55-59
<https://en.wikipedia.org/wiki/Phase_detector>
<https://jaunty-electronics.com/blog/2012/09/exclusive-or-xor-gate-based-phase-detector/>
<http://memo.cgu.edu.tw/jtkuo/files/eelab%202014(iii)/1230_lab12_expxx_phaselockedloop.pdf>
and many, many, many others.
Best regards,
Charles
_______________________________________________
time-nuts mailing list -- [email protected]
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
_______________________________________________
time-nuts mailing list -- [email protected]
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
_______________________________________________
time-nuts mailing list -- [email protected]
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
