Division by an odd factor requires clocking off both edges of the incoming clock if you wish to achieve a 50% duty cycle output. So the output duty cycle is affected by the duty cycle and response to the possibly different risetime and falltime of the incoming clock. I would think that for the best immunity from these effects you would need to use a differential amplifier to get clean rising edges from both incoming edges. But this may be too much detail ... see the following link for some examples of how to divide by odd numbers: http://www.onsemi.com/pub_link/Collateral/AND8001-D.PDF -- Bill Byrom N5BB
On Sun, Sep 27, 2015, at 11:36 AM, ed breya wrote: > I need to build an ECL divide by 3 circuit to run at about 50 MHz input. > I know there are lots of examples out there, but I vaguely recall years > ago I stumbled upon one or more that also provided more of a symmetrical > output nearly 50 percent duty factor, by using both input edges, or > reclocking with another FF. I saved the info, but of course can't find > it now that I need it - in my computers, papers, or online. Does anyone > know of these tricks, and any example circuits - this would save me some > rediscovery and design time. > > Ed > _________________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
