Hi Charles (et al), So, I did see that post, but I'm not entirely sure how it works. If I understand, the FPGA is generating the 9.7khz clock (which I can see on the test pad he indicated), running it through some logic to square it up, then a low pass filter, then into the op-amp similar to this: http://ww1.microchip.com/downloads/en/AppNotes/00538c.pdf (and this: http://www.ti.com/lit/an/spraa88a/spraa88a.pdf) ?
So where does the 5v reference play in? I see on the newer models apparently U14 is fed power by that reference? Maybe that's the same here... Anyway, I lifted the 5v reference pin and fed the pad with the 5v supply. While it did keep positive, it was still being pulled down to just over 3v. So wherever that pin goes is pulling a fair amount of current. The 5v reference pin, while lifted, hovered just a few millivolts above 0v, and the disciplining of the OCXO remained the same 26hz high. I'm starting to think the LT1014 is also bad, which I'm glad I have one on order along with the reference. Just in case, I did reflow all the pins on the opamp, reference, associated transistors, and the flip flop (U14) (which looks to be okay given its input and output appear to be there) I'm starting to think the previous owner accidentally plugged -12v into the +12v supply (maybe fully reversing them)? That doesn't explain the MAX232 dying, but it would probably nuke the 5v reference and the opamp. Mixing up any of the others (swapping +/- 12v for 5v) probably would have left far more casualties. :/ Reconnecting the 5v ref pin returned it right back to -0.6v (yes, negative). The FPGA, I'd think, is probably okay given it's putting out a good 9.7khz. But I haven't ever troubleshot one of those before, so maybe part of it could be dead. :( Anything else I might want to look at? And thanks for all the responses! Ryan Stasel IT Operations Manager, SOJC University of Oregon Sent from my iPhone On Mar 29, 2016, at 02:01, Charles Steinmetz <[email protected]<mailto:[email protected]>> wrote: Ryan wrote: Also confusing is the quad op-amp seems to be saturated at the negative rail. I can see this Opamp feeds the adjust pin on the OCXO, but I'm not sure what feeds it. Guessing the FPGA? I still can't find the DAC all I see are these pictures [ ] but the pictures aren't of the DAC, unless the DAC is a resistor ladder (hadn't thought of that until now). Now I'm starting to realize this is probably the case. Stewart Cobb described the operation of the DAC (actually, PWM) in a post on Nov 2, 2013 ("Subject: [time-nuts] Thunderbolt tuning DAC theory of operation"). Check the list archive. Does it seem likely the 5V reference is dead? If the output is at 0.6v, as you say, then either the reference chip is bad or something on the load side of the 5v reference bus is drawing too much current and dragging it down. I don't really want to just lift the output of the 5V reference and leave whatever it feeds floating. Why not lift the output pin and connect the PC trace to the 5v logic supply through, say, 470 ohms? This will limit the current through the load to ~10mA if the load side is bad. Then measure the voltages on the referrence output pin and the PC trace. One or the other should be ~5v (unless the reference and the load side are both bad). The one that is low will tell you which side (reference or load) is the problem. Best regards, Charles _______________________________________________ time-nuts mailing list -- [email protected]<mailto:[email protected]> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
