:) yes, it is.
Basically I need to sync two signals at a variable frequency centered at
about 10MHz, for 8 hours. The actual bandwidth depends because there
will be a variable number of harmonics on such signal.
The data logging system is for the intensity interferometer, and it
needs an error management like the above, it will use a PLL of an FPGA
that pulls up the frequency from the main oscillator into 400MHz, the
FPGA's PLL is very flexible, so the main XT frequency may not be
obligatory at 10MHz.
Regards,
Ilia.
Il 26/04/2016 00:12, Bruce Griffiths ha scritto:
There's no spec for th 10MHz option you originally specified.What's the jitter
bandwidth of interest?
Still need a spec for the data logging system timebase error.This is for your
intensity interferometer?
Bruce
On Tuesday, 26 April 2016 10:00 AM, Ilia Platone <[email protected]>
wrote:
I haven't bought anything yet, so feel free to recommend me any
components/setup.
here is the datasheet I am referring to:
http://www.foxonline.com/pdfs/FVXO_HC53.pdf
It contains some informations about phase jitter on page 5.
The
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
Let me know,
Ilia.
Il 25/04/2016 22:51, Bruce Griffiths ha scritto:
On Monday, April 25, 2016 09:41:57 PM Ilia Platone wrote:
Hi all,
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
and a Telit Jupiter
<http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en>SE880<http
://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en>, this serves
for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
Thank you,
Ilia.
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What are the timing specifications for the data logging system?
Without this data, its not possible to decide if the proposed GPSDO will meet
these specifications.
Whist its possible to construct a GPSDO using almost any crystal controlled
oscillator, the timing performance will vary widely.
The datasheet for the Fox VCXO you selected does not specify the phasenoise,
jitter or ADEV for the 10MHZ option.
Bruce
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--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999
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