The aged 16550 has various timeouts so an interrupt is triggered with a partially full buffer even if it is below the interrupt threshold. For implementations which do not do that, I assume they intend for the UART to be polled regularly.
On Mon, 18 Jul 2016 23:42:34 -0400, you wrote: >I can't speak for linux, but I have been bitten by FIFO watermark >interrupts on micros before. If you set an interrupt for a 3/4 full FIFO, >the last one or two characters will sit in the receive buffer and never >trigger the RX interrupt. For a command -> response device which doesn't >have a constant data-stream, It isn't until a PC application resends the >command sequence that enough characters are in the FIFO to trigger the >watermark interrupt. The easy fix was to interrupt on any single character >being available, but would have been nice to have a timeout interrupt on a >partially full FIFO. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.