Hi,
The J06 P-59992A time interval calibrator is not only there to calibrate
time offsets, but also offsets in trigger point. HP has a nice patent
which describes it all.
I also got one, found it on ebay.
Cheers,
Magnus
On 07/09/2017 01:18 AM, Bob kb8tq wrote:
Hi
Good means whatever the 5313x needs for calibration. If that is four signals
that are
crossing zero within < 10 ps of the “correct time” then that is the definition
of good in this case.
Rise time delay, fall time delay are rarely the same in logic gates.
Propagation inside a chip to
point A may well be different by nanoseconds relative to the propagation to a
very similar
point B. All of that would mess up a signal that *might* need to be 50/50 to
within 10 ps or
a second signal that must cross zero half way in-between (also to within 10 ps).
If you want to have a lot of fun with this, pull out the timing analysis tool
for your favorite
FPGA and start fiddling around.
Bob
On Jul 8, 2017, at 5:53 PM, Hal Murray <[email protected]> wrote:
[email protected] said:
The PIC dividers are good to a couple ps. I suspect the larger issue is the
PCB and wiring design.
What does "good" mean?
I'd expect the variations due to power or temperature would be easy to
measure.
Delay through classic CMOS is linear with absolute temperature and inverse
linear with supply voltage.
The classic way to get time-nuts level noise on FPGA outputs is to wiggle a
nearby pin. That shouldn't be a problem with a dedicated PIC but would
probably show up if you are generating multiple frequencies.
--
These are my opinions. I hate spam.
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