The attached circuit is suitable for testing the PN of various CMOS inveters
etc used as sine to CMOS converters.
Just adjust the input LC network and resistors to suit the source, frequency,
power and CMOS device Vcc.
Select the resistor in series with the CMOS output to produce a total series R
~ 68 ohms when the CMOS device output R is included. Some fast CMOS devices
(esp clock drivers) have an output R close to 50 ohms as they are intended to
drive 50 ohm source terminated transmision lines.
Output network LC values are selected to suit the output frequency of the CMOS
device.
Bruce
> On 04 March 2018 at 10:56 Bruce Griffiths <bruce.griffi...@xtra.co.nz> wrote:
>
>
> Hystersis (exhibited by 74xx14 devices) results in AM to PM conversion which
> increases as the amount of hysteresis increases.
>
>
> Bruce
>
> >
> > On 04 March 2018 at 10:34 Bruce Griffiths <bruce.griffi...@xtra.co.nz>
> > wrote:
> >
> > Ideally one should use a Collins style optimised cascade of increasing
> > bandwidth and gain limiting stages. The LTC6957 with its selectable input
> > stage bandwidth has a performance that is comparable with the Holzworth
> > sine to CMOS "amplifier" which is better than any comparator by itself. If
> > the amplitude of the input signal is large enough (i.e. input slew rate
> > seen by the gate is large enough) the performance of a single CMOS gate can
> > be very good. However the performance of current CMOS gates degrades in
> > this application with input frequencies of 100MHz and above.
> >
> > Measuring the PN performance of CMOS gates used as sine to CMOS
> > converters is on the todo list.
> >
> > Bruce
> >
> > > >
> > > On 04 March 2018 at 06:38 "David C. Partridge"
> > > <david.partri...@perdrix.co.uk> wrote:
> > >
> > > You might consider using MC74VHC1GT14 or MC74VHC1G14 (Schmitt
> > > trigger inverting buffers) depending on the exact voltage levels.
> > >
> > > They are fast (74AC logic fast) single gate devices in SC70
> > > (SOT-353) or SOT23-5 case and can drive 25mA output if needed.
> > >
> > > I've seen documents saying that using fast logic gates can result
> > > in lower jitter/phase noise. Bruce - do you know ?
> > >
> > > David
> > >
> > > -----Original Message-----
> > > From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of
> > > Ulf Kylenfall via time-nuts
> > > Sent: 03 March 2018 17:08
> > > To: Discussion of Precise Time and Frequency Measurement
> > > Subject: [time-nuts] LT1016 as a pulse shaper...
> > >
> > > Gentlemen,
> > > I have so far been using LT1016 as a pulse shaper and also
> > > whenever I needed toconvert a sine wave into TTL Logic levels. Some
> > > hysteresis and all the decouplingand layout precautions as recommended by
> > > LT.
> > > Are there any similar or better alternatives out there that could
> > > be usedthat would provide lower jitter and that are less expenceive?
> > > Ulf Kylenfall
> > > SM6GXV
> > >
> > > _______________________________________________
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> > > >
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