On Sun, 24 Jun 2018 14:22:14 -0400
Bob kb8tq <[email protected]> wrote:
> One of the things I’ve run into doing Rb’s this way is that the spurs out of
> the DDS
> are not always the same device to device. They also change a lot with small
> tuning
> changes. The result can be a very close in spur ( like << 1 Hz) that really
> rips up
> your ADEV since it passes through all the cleanup PLL’s …. It’s a rare
> occurrence,
> but it does actually happen.
With DDS in FPGA you can work around these issues. E.g. the phase
accumulator can be arbitrary wide with moderate cost (48bit would
be in the order of 3k-8kLE) and you can employ additional techniques
to minimize spurs due to the non-linearity of the DAC.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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