Hi Half of the problem is on the digital side. The other half is on the DAC side of things. More bits / wider registers is fine for the digital stuff. Once you narrow the bit range down to feed a rational DAC problems begin to creep in. Now shove that into a DAC that does not have *perfect* linearity and even more problems crop up.
Bob > On Jun 24, 2018, at 2:57 PM, Attila Kinali <[email protected]> wrote: > > On Sun, 24 Jun 2018 14:22:14 -0400 > Bob kb8tq <[email protected]> wrote: > >> One of the things I’ve run into doing Rb’s this way is that the spurs out of >> the DDS >> are not always the same device to device. They also change a lot with small >> tuning >> changes. The result can be a very close in spur ( like << 1 Hz) that really >> rips up >> your ADEV since it passes through all the cleanup PLL’s …. It’s a rare >> occurrence, >> but it does actually happen. > > With DDS in FPGA you can work around these issues. E.g. the phase > accumulator can be arbitrary wide with moderate cost (48bit would > be in the order of 3k-8kLE) and you can employ additional techniques > to minimize spurs due to the non-linearity of the DAC. > > > Attila Kinali > -- > It is upon moral qualities that a society is ultimately founded. All > the prosperity and technological sophistication in the world is of no > use without that foundation. > -- Miss Matheson, The Diamond Age, Neil Stephenson > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://lists.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://lists.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
