Hi Anders look that
https://www.analog.com/media/ru/training-seminars/tutorials/MT-086.pdf 73 KJ6UHN Alex On 2/1/2019 10:11 AM, Anders Wallin wrote:
Hi all, is there are rule-of-thumb or simple paper/presentation of how to choose PLL-gains? I have a phase-detector that gives out a slope of roughly 1 V/rad, followed by an op-amp circuit with proportional, integral, and double-integral gains summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6 ppm pull-range, from datasheet). So far it locks with only P-gain, but the phase-noise (and ADEV) shows a 'bump' somewhere between 10 and 100 Hz offset from the carrier. I tried the integrator with a time-constant of 1/16Hz using R 100k C 100n, but it wouldn't lock. The thinking was to put the integrator time-constant about where the free-running ADEV turns upwards from a 1/tau slope. So far I didn't enable the double-integrator - not sure if it's worth the trouble or not.. thanks, Anders _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. --- This email has been checked for viruses by AVG. https://www.avg.com
_______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
