I learned a useful rule of thumb design procedure for 2nd degree PLLs some time ago (I'll speak in the context of using an inverting op-amp in the loop gain/filter stage):
Step 1: Short the capacitor in the opamp's FB loop, then set the resistor so that the PLL has the desired loop bandwidth. This is the gain part of the adjustment. 2. Then set the capacitor value so that its reactance at the frequency of the loop BW is about 1/5th the resistance that you set in step 1. This is the damping setting step. 3. Then examine the overall loop behavior for its damping behavior. If there are no "hidden poles" somewhere, the above should yield pretty good results right off that bat, but a little tweaking is always fair game if you want. However, there *are* often "hidden rolloffs" (poles) somewhere, and damping behavior will be degraded. Such poles are most likely to arise in two areas- the VCO itself, or the opamp you're using. Be sure that the opamp's gain- bandwidth is much larger than required, said requirement being the product of the gain being called for in the opamp stage and the desired PLL bandwidth. And VCOs always introduce hidden poles into the loop, which are not usually well documented in the oscillator's specsheet (if at all). But with luck you won't run into either problem area for the low loop bandwidths typically desired in oscillator-cleanup PLL applications. Dana K8YUM On Fri, Feb 1, 2019 at 11:04 PM Magnus Danielson <mag...@rubidium.se> wrote: > Hej Anders, > > On 2019-02-01 19:11, Anders Wallin wrote: > > Hi all, is there are rule-of-thumb or simple paper/presentation of how to > > choose PLL-gains? > > > > I have a phase-detector that gives out a slope of roughly 1 V/rad, > followed > > by an op-amp circuit with proportional, integral, and double-integral > gains > > summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6 > > ppm pull-range, from datasheet). > > > > So far it locks with only P-gain, but the phase-noise (and ADEV) shows a > > 'bump' somewhere between 10 and 100 Hz offset from the carrier. > > I tried the integrator with a time-constant of 1/16Hz using R 100k C > 100n, > > but it wouldn't lock. > > The thinking was to put the integrator time-constant about where the > > free-running ADEV turns upwards from a 1/tau slope. > > > > So far I didn't enable the double-integrator - not sure if it's worth the > > trouble or not.. > > OK, I can give you a more in-depth overview, but I just crash this quickly. > > Now, let's assume you have a pure phase-detector (such as a mixer), a > PI-regulator and an oscillator. > > This represents a second-degree PLL, which has two key properties: > natural frequency and damping factor. > > The natural frequency depends on the loop bandwidth as it goes though > the integrator path and the I factor. > > The I factor is proportional to the natural frequency in square. > > The damping factor depents on the balance between the I and P factors, > in fact the P factor is proportional to the natural frequency and > damping factor multiplied. > > I've derived the formulas multiple times here on time-nuts, but if you > need further details, please let me know. Happy to discuss off-list. > > The loop-gain, as it goes through the integrator path, will decide the > bandwidh of the PLL and thus the time-constants of the PLL. > > The loop-gain, as it goes through the proportional path, decides the > damping factor and hence the bump of the PLL. > > In general, you want to make sure your damping constant is high enough > and thus avoid the bump, and then dimension the filter bandwidth to > bring the best balance between the reference oscillators phase-noise and > the locked oscillators phase-noise. Essentially you overlay the > phase-plots of reference and locked oscillator, and where they cross you > put your cross-over bandwidth, as the PLL will low-pass filtet the > reference oscillator phase-noise and high-pass filter the > locked-oscillator phase-noise. The resonance due to lack of damping will > exagerate the response at the cross-over frequency. > > Uhm, this may sound a bit uncoherently, but it all fits together if you > play around. > > For the double-integration path, you need to be careful as the > root-locus does not guarantee a stable system, as the complex pole-pair > can move over to the right-hand side and hence severely unstable. > > I can make a few recommended readings. The TI application note > referenced isn't bad, but there is a few books to look at. The TI > app-note does however cover some of the field the following references > miss out on. > > The Best book may be a good crash-coarse, but ends up not being good at > teach the basics. It may be good for crashing into the field of PLLs, > and for some things it's a very handy reference, but for others... not > so much. > > The Gardner book is the one book I recommend. Few books has core > knowledge so well compressed. If one only gets one book, this would be > the one I would recommend. > > The Wolaver book is really a great complementary book. Great on it's own > merrits. > > I end up using all three to cover enough aspects of the field. I should > probably be using the TI app-note a little more. > > Let's talk about your specific problem and I will help you more. > > Cheers, > Magnus > > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
