Let's put the Bert vs. Dana misunderstanding aside.
To me the key feature in Bert's photo is the Dallas/Maxim digital delay
chip. Look carefully and see the DS1023-50, which is an 8-bit
programmable delay line (~0 to ~127 ns in 0.5 ns steps). This is a
technique used to remove sawtooth error without requiring a ns or sub-ns
TIC and a PC.
The trick: before each 1PPS the delay line is latched with the
appropriately signed and scaled sawtooth correction number so that when
the 1PPS arrives the leading edge is physically (electronically) delayed
by exactly the right number of compensating ns. If you look inside one
of Rick Hambly's GPS clocks [1] you will see this. Each second a PIC
reads the binary sawtooth message from the receiver and programs the
delay line just in time for the next 1PPS. The result is a sawtooth-free
1PPS without requiring a TIC or a PC. The idea has been around for 20
years, the era of the Motorola Oncore VP receiver.
The performance of this "hardware" solution to sawtooth correction is
simpler and nearly as good as the more complex "software" solution
that's used today. For comparison plots see page 35 of:
https://www.haystack.mit.edu/workshop/TOW2017/files/Seminars/tow-time2017.pdf
The plot is beautiful. The reason this delay line technique isn't used
much anymore is that AFAIK the Dallas chips are no longer produced. So
almost every uses s/w sawtooth correction now.
/tvb
[1] https://www.cnssys.com/cnsclock/CNSClockII.php
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