Doug, > Situation A : Board is continuous between trace A > and trace B. That is to say, there > is FR4 material between the traces. > > ---------------------- > ------ ------ > | A | | B | > ------ ------ > ----------------------
We have treated this as a cemented joint and have achieved an electric strength >5kV for a 6 thou spacing (inner layers only). It's the outer layers where creepage (and to some extend clearance) becomes applicable with around 1kV for a 6thou spacing. The creepage increased from 1kV @ 6thou to 2.3kV at 60thou whereas the clearance increased from 980V @ 6thou to 5kV @ 54thou. Different samples gave slightly different results, this may be to do with the fibreglass weave grain and surface contamination. > > Situation B : Board is NOT continuous between trace A > and trace B. That is to say, there is an > air gap cut through the board between > the traces leaving the traces exposed. > > --------+ +----------- > ------| |------ > | A | | B | > ------| |------ > --------+ +----------- > > Clearly, even on an unpopluated board fab, > Situation B is strictly a clearance issue. Haven't used this scenario and can't think when we would, but yes in this situation clearance is more applicable than creepage, dependant upon the distances involved. > I assume you're talking 1 or 2 oz copper for your traces? Generally 1oz but greater on PSU's, have you found that the thickness alters the creepage/clearance greatly? What relevance are the creepage distances quoted in IEC 664-1 Table 4 column 2 for printed circuit material, do these assume a CTI of >600 (Material Group I)?, if so this has not been stated. The IEC 664-1 creepage figures differ greatly from those in IEC 950 for PCB material. Where did these come from and what can they be used for? Are there any creepage and clearance experts out there? Regards Richard Steele Equipment Engineering Fujitsu telecommunications Europe limited
