From: Ye Li <ye...@nxp.com>
When write DDR mode registers, should poll the MD_EN bit of
DDR_SDRAM_MD_CNTL to ensure the MRW command is issued by controller.
Otherwise, it may have problem that following MRS overwrite the
previous one which has not been issued yet.
Signed-off-by: Ye Li <ye...@nxp.com>
Reviewed-by: Jacky Bai <ping....@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
drivers/ddr/imx/imx9/ddr_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index
5b0ad773875da9f6a57faa8c618b232056d1e702..7bade70bd0a1ca4d205ff4fb8525511188cb504f
100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -291,6 +291,8 @@ void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
regval = (cs_sel << 28) | (opcode << 6) | (mr);
writel(regval, REG_DDR_SDRAM_MD_CNTL);
setbits_le32(REG_DDR_SDRAM_MD_CNTL, BIT(31));
+ while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000)
+ ;
check_ddrc_idle();
}
--
2.35.3
