On Sun, Jul 27, 2025 at 11:14 PM Peng Fan (OSS) <peng....@oss.nxp.com> wrote:
>
> From: "Tom.zheng" <haidong.zh...@nxp.com>
No need to enclose the name with " and put a dot between the names.
>
> If the DDR data INIT bit is set, and ddr is running at low frequency,
> need to make sure DDR initialization complete before continue.
> Otherwise, unpredictable behavior when inline ECC id enabled.
>
> Signed-off-by: Tom.zheng <haidong.zh...@nxp.com>
Tom Zheng (without the dot in the middle).
> Signed-off-by: Jacky Bai <ping....@nxp.com>
> Reviewed-by: Peng Fan <peng....@nxp.com>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> ---
> arch/arm/include/asm/arch-imx9/ddr.h | 1 +
> drivers/ddr/imx/imx9/ddr_init.c | 18 +++++++++++++++++-
> 2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-imx9/ddr.h
> b/arch/arm/include/asm/arch-imx9/ddr.h
> index
> a8e3f7354c7b3557b14e6f81c93d7c719171aa4d..31c420198f667f0dd334c896fe9ab0b06797641e
> 100644
> --- a/arch/arm/include/asm/arch-imx9/ddr.h
> +++ b/arch/arm/include/asm/arch-imx9/ddr.h
> @@ -19,6 +19,7 @@
> #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
> #define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
> #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
> +#define REG_DDR_SDRAM_CFG2 (DDR_CTL_BASE + 0x114)
> #define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
> #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
> #define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260)
> diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
> index
> 7bade70bd0a1ca4d205ff4fb8525511188cb504f..5a134dda78a331c21d4a75b2369c5b9314028bbc
> 100644
> --- a/drivers/ddr/imx/imx9/ddr_init.c
> +++ b/drivers/ddr/imx/imx9/ddr_init.c
> @@ -342,9 +342,11 @@ int ddr_init(struct dram_timing_info *dram_timing)
> unsigned int initial_drate;
> struct dram_timing_info *saved_timing;
> void *fsp;
> - int ret;
> + int i, ret;
> u32 mr12, mr14;
> u32 regval;
> + struct dram_cfg_param *ddrc_cfg;
> + unsigned int ddrc_cfg_num;
>
> debug("DDRINFO: start DRAM init\n");
>
> @@ -387,6 +389,20 @@ int ddr_init(struct dram_timing_info *dram_timing)
>
> check_ddrc_idle();
>
> + /* if DRAM Data INIT set, wait it be completed */
> + ddrc_cfg = dram_timing->ddrc_cfg;
> + ddrc_cfg_num = dram_timing->ddrc_cfg_num;
> + for (i = 0; i < ddrc_cfg_num; i++) {
> + if (ddrc_cfg->reg == REG_DDR_SDRAM_CFG2) {
> + if (ddrc_cfg->val & 0x10) {
> + while (readl(REG_DDR_SDRAM_CFG2) & 0x10)
> + ;
Consider using readl_poll_timeout() here as well.
