Yes i am where that there is no NAND controller so did that already and i
see stuff happing on my scope. I thought that i was missing something for
this flash chip.
I am attaching my nand controllor code could any body tell me if i am
missing something for the 405EP i am new to the 405EP processor... But i
worked on did processors that i had nand setup and it was a lot lets work.
Most cases all it was just overwrite the ready and hwcontrol functions.
Pawel
On Thu, Mar 13, 2008 at 3:38 PM, Stefan Roese <[EMAIL PROTECTED]> wrote:
> On Thursday 13 March 2008, Pawel Pastuszak wrote:
> > I trying to get nand flashing working for powerpc 405ep, i am currently
> > having some problem with read and writing to the flash. I was wondering
> if
> > anybody got the MT29F2G08 flash working.
>
> Sure. It's working on multiple 405EP implementation I have seen so far.
> Perhaps not exactly with the NAND chips you mentioned. But that shouldn't
> really matter. You are aware that the 405EP doesn't have a build-in NAND
> controller and you need minimal external logic to connect a NAND chip to
> the
> 405EP?
>
> Best regards,
> Stefan
>
> =====================================================================
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED]
> =====================================================================
>
/*
* (C) Copyright 2006 Aubrey.Li, [EMAIL PROTECTED]
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <linux/mtd/ndfc.h>
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#define CONCAT(a,b,c,d) a ## b ## c ## d
#define PORT(a,b) CONCAT(pPORT,a,b,)
#ifndef CONFIG_NAND_GPIO_PORT
#define CONFIG_NAND_GPIO_PORT F
#endif
/*
* hardware specific access to control-lines
*/
static u8 hwctl;
#define readb(addr) (u8)(*(volatile u8 *)(addr))
#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
static void my_hwcontrol(struct mtd_info *mtd, int cmd)
{
//register struct nand_chip *this = mtd->priv;
switch (cmd) {
case NAND_CTL_SETCLE:
//this->IO_ADDR_W = CFG_NAND_BASE + my_NAND_CLE;
//writeb((CFG_NAND_BASE + my_NAND_CLE) | 0x1, (CFG_NAND_BASE +
my_NAND_CLE));
hwctl |= 0x1;
break;
case NAND_CTL_CLRCLE:
//this->IO_ADDR_W = CFG_NAND_BASE;
//writeb((CFG_NAND_BASE + my_NAND_CLE) & ~0x1, (CFG_NAND_BASE +
my_NAND_CLE));
hwctl &= ~0x1;
break;
case NAND_CTL_SETALE:
//this->IO_ADDR_W = CFG_NAND_BASE + my_NAND_ALE;
//writeb((CFG_NAND_BASE + my_NAND_ALE) | 0x2, (CFG_NAND_BASE +
my_NAND_ALE));
hwctl |= 0x2;
break;
case NAND_CTL_CLRALE:
//writeb((CFG_NAND_BASE + my_NAND_ALE) & ~0x2, (CFG_NAND_BASE +
my_NAND_ALE));
//this->IO_ADDR_W = CFG_NAND_BASE;
hwctl &= ~0x2;
break;
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
}
//this->IO_ADDR_R = this->IO_ADDR_W;
//printf("Nand: %x\n", this->IO_ADDR_R);
//writeb(hwctl, CFG_NAND_BASE);
}
static void my_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
if (hwctl & 0x1) {
printf("Writing-C: %x - %x\n",( base + NDFC_CMD), byte );
out_8((u8 *)(base + NDFC_CMD), byte);
}else if (hwctl & 0x2) {
printf("Writing-A: %x - %x\n",(u8*)( base + NDFC_ALE), byte);
out_8((u8 *)(base + NDFC_ALE), byte);
} else {
printf("Writing-D: %x - %x\n",( base + NDFC_DATA), byte);
out_8((u8 *)(base + NDFC_DATA), byte);
}
}
static u_char my_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
printf("Reading: %x - %x\n", this->IO_ADDR_W, in_8((u8 *)(base +
NDFC_DATA)));
return (in_8((u8 *)(base + NDFC_DATA)));
}
int my_device_ready(struct mtd_info *mtd)
{
ulong rb_gpio_pin;
if (in32(GPIO0_IR) & CFG_NAND_RDY)
return 1;
return 0;
}
/*
* Speedups for buffer read/write/verify
*
* NDFC allows 32bit read/write of data. So we can speed up the buffer
* functions. No further checking, as nand_base will always read/write
* page aligned.
*/
static void my_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
uint32_t *p = (uint32_t *) buf;
for (;len > 0; len -= 4)
*p++ = in_be32((u32 *)(base + NDFC_DATA));
}
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
* nand_scan about special functionality. See the defines for further
* explanation
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
int board_nand_init(struct nand_chip *nand)
{
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
nand->hwcontrol = my_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->dev_ready = my_device_ready;
nand->chip_delay = 30;
nand->write_byte = my_write_byte;
nand->read_buf = my_read_buf;
nand->read_byte = my_read_byte;
return 0;
}
#endif
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