Stefan,
My implemention is using the adddress for ALE/CLE. I did get it working and
works great.
I am providing the code that i have my nand flash working with.
P.S. Stefan thanks for the help.
Pawel
On Fri, Mar 14, 2008 at 3:15 AM, Stefan Roese <[EMAIL PROTECTED]> wrote:
> On Thursday 13 March 2008, Pawel Pastuszak wrote:
> > Yes i am where that there is no NAND controller so did that already and
> i
> > see stuff happing on my scope. I thought that i was missing something
> for
> > this flash chip.
> >
> > I am attaching my nand controllor code could any body tell me if i am
> > missing something for the 405EP i am new to the 405EP processor... But
> i
> > worked on did processors that i had nand setup and it was a lot lets
> work.
>
> From looking at the code, I wonder *how* you did implement the external
> logic
> on your board. I would have thought you connected some of the NAND control
> pins to 405EP GPIO's. But this doesn't seem to be the case. You are
> accessing
> the CMD/ALE singals at different addresses. So what exactly is you
> external
> NAND controller logic?
>
> If not, I suggest you take a look at:
>
> board/esd/common/esd405ep_nand.c
>
> This is an 405EP NAND implementation with external logic and signals
> attached
> to GPIO's.
>
> Best regards,
> Stefan
>
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/*
* (C) Copyright 2006 Aubrey.Li, [EMAIL PROTECTED]
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <linux/mtd/ndfc.h>
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
/*
* hardware specific access to control-lines
*/
static u8 hwctl=0;
static void my_hwcontrol(struct mtd_info *mtd, int cmd)
{
register struct nand_chip *this = mtd->priv;
switch (cmd) {
case NAND_CTL_SETCLE:
hwctl |= my_NAND_CLE;
break;
case NAND_CTL_CLRCLE:
hwctl &= ~my_NAND_CLE;
break;
case NAND_CTL_SETALE:
hwctl |= my_NAND_ALE;
break;
case NAND_CTL_CLRALE:
hwctl &= ~my_NAND_ALE;
break;
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
}
}
static void my_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
if (hwctl & my_NAND_CLE) {
out_8((u8 *)(CFG_NAND_BASE + my_NAND_CLE), byte);
}else if (hwctl & my_NAND_ALE) {
out_8((u8 *)(CFG_NAND_BASE + my_NAND_ALE), byte);
}
}
static u_char my_read_byte(struct mtd_info *mtdinfo)
{
return in_8((u8 *)(CFG_NAND_BASE));
}
int my_device_ready(struct mtd_info *mtd)
{
ulong rb_gpio_pin;
if (in32(GPIO0_IR) & CFG_NAND_RDY)
return 1;
return 0;
}
/*
* Speedups for buffer read/write/verify
*
* NDFC allows 32bit read/write of data. So we can speed up the buffer
* functions. No further checking, as nand_base will always read/write
* page aligned.
*/
static void my_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
// struct nand_chip *this = mtdinfo->priv;
// ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
uint32_t *p = (uint32_t *) buf;
for (;len > 0; len -= 4)
*p++ = in_be32((u32 *)(CFG_NAND_BASE));
}
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
* nand_scan about special functionality. See the defines for further
* explanation
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
int board_nand_init(struct nand_chip *nand)
{
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
nand->hwcontrol = my_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->dev_ready = my_device_ready;
nand->chip_delay = 30;
nand->write_byte = my_write_byte;
nand->read_buf = my_read_buf;
nand->read_byte = my_read_byte;
return 0;
}
#endif
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