On Jul 17, 2013, at 6:42 AM, Albert ARIBAUD <[email protected]> wrote:
> I understand the symptom. What I don't undestand is how come NAND > does not keep its data lines in high impedance when its chip select is > inactive, which it is when DDR is being accessed. Chip selects prevent contention but they do not make the load vanish. A deselected chip is not electrically the same as a non-populated chip, especially at high frequencies. Think of it another way. CMOS pins that are input-only are always high-z but they still must be counted as a load when adding up the fan out seen by the upstream output driver. -Mike _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
