Hi Michael, On Wed, 17 Jul 2013 07:27:36 -0400, Michael Cashwell <[email protected]> wrote:
> On Jul 17, 2013, at 6:42 AM, Albert ARIBAUD <[email protected]> wrote: > > > I understand the symptom. What I don't undestand is how come NAND > > does not keep its data lines in high impedance when its chip select is > > inactive, which it is when DDR is being accessed. > > Chip selects prevent contention but they do not make the load vanish. > A deselected chip is not electrically the same as a non-populated chip, > especially at high frequencies. > > Think of it another way. CMOS pins that are input-only are always high-z > but they still must be counted as a load when adding up the fan out seen > by the upstream output driver. They must be counted as load alright, I understand this. But that leaves / leads to some questions: - how come the issue never appeared so far? If this is so basic a problem, I would have expected it to show up as soon as the SoC gets frequent use. - doesn't the driving lines' fan-out take this load into account? Again, I would expect a device's drive to be strong enough to overcome a few Hi-Zs, since that's an expected type of load. - why is the issue not symmetric? Techno's CMOS or CMOS-like, I guess, so there is no reason to pull up rather than down. Unless there are pulldowns in the NAND or elsewhere, but then it's not Hi-Z any more. > -Mike Amicalement, -- Albert. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
