On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: > If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this > means that DRAM is currently in self-refresh mode and retaining the old > data. Since we have no idea what to do in this situation yet, just set this > register to 0 and initialize DRAM in the same way as on any normal reboot > (discarding whatever was stored there). > > This part of code was apparently used by the Allwinner boot0 bootloader to > handle resume from the so-called super-standby mode. But this particular > code got somehow mangled on the way from the boot0 bootloader to the > u-boot-sunxi bootloader and has no chance of doing anything even remotely > sane. For example: > 1. in the original boot0 code we had "mctl_write_w(SDR_DPCR, 0x16510000)" > (write to the register) and in the u-boot it now looks like > "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the register) > 2. in the original boot0 code it was issuing three commands "0x12, 0x17, 0x13" > (Self-Refresh entry, Self-Refresh exit, Refresh), but in the u-boot they > have become "0x12, 0x12, 0x13" (Self-Refresh entry, Self-Refresh entry, > Refresh) > > Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Ian Campbell <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
