On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: > Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires > to wait for additional 500 us after the RESET pin is de-asserted. > > The DRAM controller takes care of this delay by itself, using a > configurable counter in the SDR_IDCR register. This works in the same > way on sun4i/sun5i/sun7i hardware (even the default register value > 0x00c80064 is identical). Except that the counter is ticking a bit > slower on sun7i (3 DRAM clock cycles instead of 2), resulting in > longer actual delays for the same settings. > > This patch keeps the old code and only removes the CONFIG_SUN7I ifdef. > But maybe we should drop all of this and just add 'udelay(500)' after > the DDR3 reset without bothering to play with these undocumented > registers.
I'm happy to go with whichever you think is better. > Another interesting observation is that the u-boot-sunxi code (derived > from the Allwinner boot0) did not configure the SDR_IDCR register > for sun4i/sun5i, but performed the DDR3 reset very early. Possibly > resulting in a sufficient time gap between the DDR3 reset and the DDR3 > initialization steps. > > Signed-off-by: Siarhei Siamashka <[email protected]> Acked-by: Ian Campbell <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
