On 12/08/2015 11:40, Peng Fan wrote: > To i.MX6SX/UL, two ethernet interfaces are supported. > Add ENET2 clock support: > 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. > To value 1, only i.MX6SX/UL can pass the check. > 2. Modify board code who use this api to follow new api prototype. > > Signed-off-by: Peng Fan <[email protected]> > Cc: Heiko Schocher <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: Stefan Roese <[email protected]> > Cc: Nikolaos Pasaloukos <[email protected]> > Cc: Stefano Babic <[email protected]> > --- > > Changes v2: > Addressed Fabio's comments. Using "fec_id == 0", but not "0 == fec_id". > > arch/arm/cpu/armv7/mx6/clock.c | 23 ++++++++++++++++++----- > arch/arm/include/asm/arch-mx6/clock.h | 2 +- > arch/arm/include/asm/arch-mx6/crm_regs.h | 6 ++++++ > board/aristainetos/aristainetos-v1.c | 2 +- > board/barco/platinum/platinum_picon.c | 2 +- > board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +- > board/freescale/mx6slevk/mx6slevk.c | 2 +- > board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- > board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- > 9 files changed, 31 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index 9cf4eec..ba6cc75 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num) > #endif > > #ifdef CONFIG_FEC_MXC > -int enable_fec_anatop_clock(enum enet_freq freq) > +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) > { > u32 reg = 0; > s32 timeout = 100000; > @@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq) > if (freq < ENET_25MHZ || freq > ENET_125MHZ) > return -EINVAL; > > - reg = readl(&anatop->pll_enet); > - reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; > - reg |= freq; > + if (fec_id == 0) { > + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; > + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); > + } else if (fec_id == 1) { > + /* Only i.MX6SX/UL support ENET2 */ > + if (!(is_cpu_type(MXC_CPU_MX6SX) || > + is_cpu_type(MXC_CPU_MX6UL))) > + return -EINVAL; > + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; > + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); > + } else { > + return -EINVAL; > + } > > if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || > (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { > @@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq) > } > > /* Enable FEC clock */ > - reg |= BM_ANADIG_PLL_ENET_ENABLE; > + if (fec_id == 0) > + reg |= BM_ANADIG_PLL_ENET_ENABLE; > + else > + reg |= BM_ANADIG_PLL_ENET2_ENABLE; > reg &= ~BM_ANADIG_PLL_ENET_BYPASS; > writel(reg, &anatop->pll_enet); > > diff --git a/arch/arm/include/asm/arch-mx6/clock.h > b/arch/arm/include/asm/arch-mx6/clock.h > index 7b3bbb8..2b220d6 100644 > --- a/arch/arm/include/asm/arch-mx6/clock.h > +++ b/arch/arm/include/asm/arch-mx6/clock.h > @@ -64,7 +64,7 @@ int enable_pcie_clock(void); > int enable_i2c_clk(unsigned char enable, unsigned i2c_num); > int enable_spi_clk(unsigned char enable, unsigned spi_num); > void enable_ipu_clock(void); > -int enable_fec_anatop_clock(enum enet_freq freq); > +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); > void enable_enet_clk(unsigned char enable); > void enable_qspi_clk(int qspi_num); > void enable_thermal_clk(void); > diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h > b/arch/arm/include/asm/arch-mx6/crm_regs.h > index fe75da4..10306cd 100644 > --- a/arch/arm/include/asm/arch-mx6/crm_regs.h > +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h > @@ -1052,6 +1052,12 @@ struct mxc_ccm_reg { > #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ > (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) > > +/* ENET2 for i.MX6SX/UL */ > +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 > +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C > +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ > + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) > + > #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 > #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 > #define BP_ANADIG_PFD_480_PFD3_FRAC 24 > diff --git a/board/aristainetos/aristainetos-v1.c > b/board/aristainetos/aristainetos-v1.c > index d6a7614..b8fed2e 100644 > --- a/board/aristainetos/aristainetos-v1.c > +++ b/board/aristainetos/aristainetos-v1.c > @@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis) > /* clear gpr1[14], gpr1[18:17] to select anatop clock */ > clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); > > - ret = enable_fec_anatop_clock(ENET_50MHZ); > + ret = enable_fec_anatop_clock(0, ENET_50MHZ); > if (ret) > return ret; > > diff --git a/board/barco/platinum/platinum_picon.c > b/board/barco/platinum/platinum_picon.c > index b2eab76..0384a26 100644 > --- a/board/barco/platinum/platinum_picon.c > +++ b/board/barco/platinum/platinum_picon.c > @@ -148,7 +148,7 @@ int platinum_setup_enet(void) > /* set GPIO_16 as ENET_REF_CLK_OUT */ > setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); > > - return enable_fec_anatop_clock(ENET_50MHZ); > + return enable_fec_anatop_clock(0, ENET_50MHZ); > } > > int platinum_setup_i2c(void) > diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c > b/board/freescale/mx6qsabreauto/mx6qsabreauto.c > index 98602f8..7c0e90a 100644 > --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c > +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c > @@ -361,7 +361,7 @@ static void setup_fec(void) > * select ENET MAC0 TX clock from PLL > */ > imx_iomux_set_gpr_register(5, 9, 1, 1); > - enable_fec_anatop_clock(ENET_125MHZ); > + enable_fec_anatop_clock(0, ENET_125MHZ); > } > > setup_iomux_enet(); > diff --git a/board/freescale/mx6slevk/mx6slevk.c > b/board/freescale/mx6slevk/mx6slevk.c > index 7c18c90..98e3ef0 100644 > --- a/board/freescale/mx6slevk/mx6slevk.c > +++ b/board/freescale/mx6slevk/mx6slevk.c > @@ -279,7 +279,7 @@ static int setup_fec(void) > /* clear gpr1[14], gpr1[18:17] to select anatop clock */ > clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); > > - return enable_fec_anatop_clock(ENET_50MHZ); > + return enable_fec_anatop_clock(0, ENET_50MHZ); > } > #endif > > diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c > b/board/freescale/mx6sxsabresd/mx6sxsabresd.c > index d58a79a..ffc0046 100644 > --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c > +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c > @@ -170,7 +170,7 @@ static int setup_fec(void) > reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; > writel(reg, &anatop->pll_enet); > > - return enable_fec_anatop_clock(ENET_125MHZ); > + return enable_fec_anatop_clock(0, ENET_125MHZ); > } > > int board_eth_init(bd_t *bis) > diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c > b/board/solidrun/mx6cuboxi/mx6cuboxi.c > index 9b1ecf0..8247e43 100644 > --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c > +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c > @@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis) > struct mii_dev *bus; > struct phy_device *phydev; > > - int ret = enable_fec_anatop_clock(ENET_25MHZ); > + int ret = enable_fec_anatop_clock(0, ENET_25MHZ); > if (ret) > return ret; > >
Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected] ===================================================================== _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
