Add i.MX6DQL dtsi support from Linux.

Cc: Peng Fan <peng....@nxp.com>
Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <fabio.este...@nxp.com>
Cc: Matteo Lisi <matteo.l...@engicam.com>
Cc: Michael Trimarchi <mich...@amarulasolutions.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 arch/arm/dts/imx6qdl.dtsi | 1281 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 1281 insertions(+)
 create mode 100644 arch/arm/dts/imx6qdl.dtsi

diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
new file mode 100644
index 0000000..b13b0b2
--- /dev/null
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -0,0 +1,1281 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+       aliases {
+               ethernet0 = &fec;
+               can0 = &can1;
+               can1 = &can2;
+               gpio0 = &gpio1;
+               gpio1 = &gpio2;
+               gpio2 = &gpio3;
+               gpio3 = &gpio4;
+               gpio4 = &gpio5;
+               gpio5 = &gpio6;
+               gpio6 = &gpio7;
+               i2c0 = &i2c1;
+               i2c1 = &i2c2;
+               i2c2 = &i2c3;
+               ipu0 = &ipu1;
+               mmc0 = &usdhc1;
+               mmc1 = &usdhc2;
+               mmc2 = &usdhc3;
+               mmc3 = &usdhc4;
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
+               spi0 = &ecspi1;
+               spi1 = &ecspi2;
+               spi2 = &ecspi3;
+               spi3 = &ecspi4;
+               usbphy0 = &usbphy1;
+               usbphy1 = &usbphy2;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ckil {
+                       compatible = "fsl,imx-ckil", "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+
+               ckih1 {
+                       compatible = "fsl,imx-ckih1", "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
+
+               osc {
+                       compatible = "fsl,imx-osc", "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <24000000>;
+               };
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&gpc>;
+               ranges;
+
+               dma_apbh: dma-apbh@00110000 {
+                       compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+                       reg = <0x00110000 0x2000>;
+                       interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 13 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+                       #dma-cells = <1>;
+                       dma-channels = <4>;
+                       clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
+               };
+
+               gpmi: gpmi-nand@00112000 {
+                       compatible = "fsl,imx6q-gpmi-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                       reg-names = "gpmi-nand", "bch";
+                       interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "bch";
+                       clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
+                                <&clks IMX6QDL_CLK_GPMI_APB>,
+                                <&clks IMX6QDL_CLK_GPMI_BCH>,
+                                <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
+                                <&clks IMX6QDL_CLK_PER1_BCH>;
+                       clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+                                     "gpmi_bch_apb", "per1_bch";
+                       dmas = <&dma_apbh 0>;
+                       dma-names = "rx-tx";
+                       status = "disabled";
+               };
+
+               hdmi: hdmi@0120000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x00120000 0x9000>;
+                       interrupts = <0 115 0x04>;
+                       gpr = <&gpr>;
+                       clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
+                                <&clks IMX6QDL_CLK_HDMI_ISFR>;
+                       clock-names = "iahb", "isfr";
+                       status = "disabled";
+
+                       port@0 {
+                               reg = <0>;
+
+                               hdmi_mux_0: endpoint {
+                                       remote-endpoint = <&ipu1_di0_hdmi>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               hdmi_mux_1: endpoint {
+                                       remote-endpoint = <&ipu1_di1_hdmi>;
+                               };
+                       };
+               };
+
+               gpu_3d: gpu@00130000 {
+                       compatible = "vivante,gc";
+                       reg = <0x00130000 0x4000>;
+                       interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
+                                <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                <&clks IMX6QDL_CLK_GPU3D_SHADER>;
+                       clock-names = "bus", "core", "shader";
+                       power-domains = <&gpc 1>;
+               };
+
+               gpu_2d: gpu@00134000 {
+                       compatible = "vivante,gc";
+                       reg = <0x00134000 0x4000>;
+                       interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                <&clks IMX6QDL_CLK_GPU2D_CORE>;
+                       clock-names = "bus", "core";
+                       power-domains = <&gpc 1>;
+               };
+
+               timer@00a00600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x00a00600 0x20>;
+                       interrupts = <1 13 0xf01>;
+                       interrupt-parent = <&intc>;
+                       clocks = <&clks IMX6QDL_CLK_TWD>;
+               };
+
+               intc: interrupt-controller@00a01000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x00a01000 0x1000>,
+                             <0x00a00100 0x100>;
+                       interrupt-parent = <&intc>;
+               };
+
+               L2: l2-cache@00a02000 {
+                       compatible = "arm,pl310-cache";
+                       reg = <0x00a02000 0x1000>;
+                       interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+                       cache-unified;
+                       cache-level = <2>;
+                       arm,tag-latency = <4 2 3>;
+                       arm,data-latency = <4 2 3>;
+                       arm,shared-override;
+               };
+
+               pcie: pcie@0x01000000 {
+                       compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
+                       reg = <0x01ffc000 0x04000>,
+                             <0x01f00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       ranges = <0x81000000 0 0          0x01f80000 0 
0x00010000 /* downstream I/O */
+                                 0x82000000 0 0x01000000 0x01000000 0 
0x00f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 
IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gpc GIC_SPI 122 
IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gpc GIC_SPI 121 
IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gpc GIC_SPI 120 
IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
+                                <&clks IMX6QDL_CLK_LVDS1_GATE>,
+                                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
+                       clock-names = "pcie", "pcie_bus", "pcie_phy";
+                       status = "disabled";
+               };
+
+               pmu {
+                       compatible = "arm,cortex-a9-pmu";
+                       interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               aips-bus@02000000 { /* AIPS1 */
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x02000000 0x100000>;
+                       ranges;
+
+                       spba-bus@02000000 {
+                               compatible = "fsl,spba-bus", "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x02000000 0x40000>;
+                               ranges;
+
+                               spdif: spdif@02004000 {
+                                       compatible = "fsl,imx35-spdif";
+                                       reg = <0x02004000 0x4000>;
+                                       interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+                                       dmas = <&sdma 14 18 0>,
+                                              <&sdma 15 18 0>;
+                                       dma-names = "rx", "tx";
+                                       clocks = <&clks 
IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
+                                                <&clks IMX6QDL_CLK_SPDIF>, 
<&clks IMX6QDL_CLK_ASRC>,
+                                                <&clks IMX6QDL_CLK_DUMMY>, 
<&clks IMX6QDL_CLK_ESAI_EXTAL>,
+                                                <&clks IMX6QDL_CLK_IPG>, 
<&clks IMX6QDL_CLK_DUMMY>,
+                                                <&clks IMX6QDL_CLK_DUMMY>, 
<&clks IMX6QDL_CLK_SPBA>;
+                                       clock-names = "core",  "rxtx0",
+                                                     "rxtx1", "rxtx2",
+                                                     "rxtx3", "rxtx4",
+                                                     "rxtx5", "rxtx6",
+                                                     "rxtx7", "spba";
+                                       status = "disabled";
+                               };
+
+                               ecspi1: ecspi@02008000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx6q-ecspi", 
"fsl,imx51-ecspi";
+                                       reg = <0x02008000 0x4000>;
+                                       interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_ECSPI1>,
+                                                <&clks IMX6QDL_CLK_ECSPI1>;
+                                       clock-names = "ipg", "per";
+                                       dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
+                                       dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+
+                               ecspi2: ecspi@0200c000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx6q-ecspi", 
"fsl,imx51-ecspi";
+                                       reg = <0x0200c000 0x4000>;
+                                       interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_ECSPI2>,
+                                                <&clks IMX6QDL_CLK_ECSPI2>;
+                                       clock-names = "ipg", "per";
+                                       dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
+                                       dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+
+                               ecspi3: ecspi@02010000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx6q-ecspi", 
"fsl,imx51-ecspi";
+                                       reg = <0x02010000 0x4000>;
+                                       interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_ECSPI3>,
+                                                <&clks IMX6QDL_CLK_ECSPI3>;
+                                       clock-names = "ipg", "per";
+                                       dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
+                                       dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+
+                               ecspi4: ecspi@02014000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx6q-ecspi", 
"fsl,imx51-ecspi";
+                                       reg = <0x02014000 0x4000>;
+                                       interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_ECSPI4>,
+                                                <&clks IMX6QDL_CLK_ECSPI4>;
+                                       clock-names = "ipg", "per";
+                                       dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
+                                       dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+
+                               uart1: serial@02020000 {
+                                       compatible = "fsl,imx6q-uart", 
"fsl,imx21-uart";
+                                       reg = <0x02020000 0x4000>;
+                                       interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+                                                <&clks 
IMX6QDL_CLK_UART_SERIAL>;
+                                       clock-names = "ipg", "per";
+                                       dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+                                       dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+
+                               esai: esai@02024000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx35-esai";
+                                       reg = <0x02024000 0x4000>;
+                                       interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
+                                                <&clks IMX6QDL_CLK_ESAI_MEM>,
+                                                <&clks IMX6QDL_CLK_ESAI_EXTAL>,
+                                                <&clks IMX6QDL_CLK_ESAI_IPG>,
+                                                <&clks IMX6QDL_CLK_SPBA>;
+                                       clock-names = "core", "mem", "extal", 
"fsys", "spba";
+                                       dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
+                                       dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+
+                               ssi1: ssi@02028000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx6q-ssi",
+                                                       "fsl,imx51-ssi";
+                                       reg = <0x02028000 0x4000>;
+                                       interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
+                                                <&clks IMX6QDL_CLK_SSI1>;
+                                       clock-names = "ipg", "baud";
+                                       dmas = <&sdma 37 1 0>,
+                                              <&sdma 38 1 0>;
+                                       dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       status = "disabled";
+                               };
+
+                               ssi2: ssi@0202c000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx6q-ssi",
+                                                       "fsl,imx51-ssi";
+                                       reg = <0x0202c000 0x4000>;
+                                       interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
+                                                <&clks IMX6QDL_CLK_SSI2>;
+                                       clock-names = "ipg", "baud";
+                                       dmas = <&sdma 41 1 0>,
+                                              <&sdma 42 1 0>;
+                                       dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       status = "disabled";
+                               };
+
+                               ssi3: ssi@02030000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx6q-ssi",
+                                                       "fsl,imx51-ssi";
+                                       reg = <0x02030000 0x4000>;
+                                       interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
+                                                <&clks IMX6QDL_CLK_SSI3>;
+                                       clock-names = "ipg", "baud";
+                                       dmas = <&sdma 45 1 0>,
+                                              <&sdma 46 1 0>;
+                                       dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       status = "disabled";
+                               };
+
+                               asrc: asrc@02034000 {
+                                       compatible = "fsl,imx53-asrc";
+                                       reg = <0x02034000 0x4000>;
+                                       interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
+                                               <&clks IMX6QDL_CLK_ASRC_MEM>, 
<&clks 0>,
+                                               <&clks 0>, <&clks 0>, <&clks 
0>, <&clks 0>,
+                                               <&clks 0>, <&clks 0>, <&clks 
0>, <&clks 0>,
+                                               <&clks 0>, <&clks 0>, <&clks 
0>, <&clks 0>,
+                                               <&clks IMX6QDL_CLK_ASRC>, 
<&clks 0>, <&clks 0>,
+                                               <&clks IMX6QDL_CLK_SPBA>;
+                                       clock-names = "mem", "ipg", "asrck_0",
+                                               "asrck_1", "asrck_2", 
"asrck_3", "asrck_4",
+                                               "asrck_5", "asrck_6", 
"asrck_7", "asrck_8",
+                                               "asrck_9", "asrck_a", 
"asrck_b", "asrck_c",
+                                               "asrck_d", "asrck_e", 
"asrck_f", "spba";
+                                       dmas = <&sdma 17 23 1>, <&sdma 18 23 
1>, <&sdma 19 23 1>,
+                                               <&sdma 20 23 1>, <&sdma 21 23 
1>, <&sdma 22 23 1>;
+                                       dma-names = "rxa", "rxb", "rxc",
+                                                       "txa", "txb", "txc";
+                                       fsl,asrc-rate  = <48000>;
+                                       fsl,asrc-width = <16>;
+                                       status = "okay";
+                               };
+
+                               spba@0203c000 {
+                                       reg = <0x0203c000 0x4000>;
+                               };
+                       };
+
+                       vpu: vpu@02040000 {
+                               compatible = "cnm,coda960";
+                               reg = <0x02040000 0x3c000>;
+                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "bit", "jpeg";
+                               clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+                                        <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
+                               clock-names = "per", "ahb";
+                               power-domains = <&gpc 1>;
+                               resets = <&src 1>;
+                               iram = <&ocram>;
+                       };
+
+                       aipstz@0207c000 { /* AIPSTZ1 */
+                               reg = <0x0207c000 0x4000>;
+                       };
+
+                       pwm1: pwm@02080000 {
+                               #pwm-cells = <2>;
+                               compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                               reg = <0x02080000 0x4000>;
+                               interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_IPG>,
+                                        <&clks IMX6QDL_CLK_PWM1>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       pwm2: pwm@02084000 {
+                               #pwm-cells = <2>;
+                               compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                               reg = <0x02084000 0x4000>;
+                               interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_IPG>,
+                                        <&clks IMX6QDL_CLK_PWM2>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       pwm3: pwm@02088000 {
+                               #pwm-cells = <2>;
+                               compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                               reg = <0x02088000 0x4000>;
+                               interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_IPG>,
+                                        <&clks IMX6QDL_CLK_PWM3>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       pwm4: pwm@0208c000 {
+                               #pwm-cells = <2>;
+                               compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                               reg = <0x0208c000 0x4000>;
+                               interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_IPG>,
+                                        <&clks IMX6QDL_CLK_PWM4>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       can1: flexcan@02090000 {
+                               compatible = "fsl,imx6q-flexcan";
+                               reg = <0x02090000 0x4000>;
+                               interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
+                                        <&clks IMX6QDL_CLK_CAN1_SERIAL>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       can2: flexcan@02094000 {
+                               compatible = "fsl,imx6q-flexcan";
+                               reg = <0x02094000 0x4000>;
+                               interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
+                                        <&clks IMX6QDL_CLK_CAN2_SERIAL>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       gpt: gpt@02098000 {
+                               compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
+                               reg = <0x02098000 0x4000>;
+                               interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
+                                        <&clks IMX6QDL_CLK_GPT_IPG_PER>,
+                                        <&clks IMX6QDL_CLK_GPT_3M>;
+                               clock-names = "ipg", "per", "osc_per";
+                       };
+
+                       gpio1: gpio@0209c000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x0209c000 0x4000>;
+                               interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 67 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio2: gpio@020a0000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x020a0000 0x4000>;
+                               interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 69 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio3: gpio@020a4000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x020a4000 0x4000>;
+                               interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 71 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio4: gpio@020a8000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x020a8000 0x4000>;
+                               interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 73 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio5: gpio@020ac000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x020ac000 0x4000>;
+                               interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio6: gpio@020b0000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x020b0000 0x4000>;
+                               interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 77 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio7: gpio@020b4000 {
+                               compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                               reg = <0x020b4000 0x4000>;
+                               interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 79 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       kpp: kpp@020b8000 {
+                               compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
+                               reg = <0x020b8000 0x4000>;
+                               interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_IPG>;
+                               status = "disabled";
+                       };
+
+                       wdog1: wdog@020bc000 {
+                               compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+                               reg = <0x020bc000 0x4000>;
+                               interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_DUMMY>;
+                       };
+
+                       wdog2: wdog@020c0000 {
+                               compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+                               reg = <0x020c0000 0x4000>;
+                               interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_DUMMY>;
+                               status = "disabled";
+                       };
+
+                       clks: ccm@020c4000 {
+                               compatible = "fsl,imx6q-ccm";
+                               reg = <0x020c4000 0x4000>;
+                               interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 88 IRQ_TYPE_LEVEL_HIGH>;
+                               #clock-cells = <1>;
+                       };
+
+                       anatop: anatop@020c8000 {
+                               compatible = "fsl,imx6q-anatop", "syscon", 
"simple-bus";
+                               reg = <0x020c8000 0x1000>;
+                               interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 54 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 127 IRQ_TYPE_LEVEL_HIGH>;
+
+                               regulator-1p1 {
+                                       compatible = "fsl,anatop-regulator";
+                                       regulator-name = "vdd1p1";
+                                       regulator-min-microvolt = <800000>;
+                                       regulator-max-microvolt = <1375000>;
+                                       regulator-always-on;
+                                       anatop-reg-offset = <0x110>;
+                                       anatop-vol-bit-shift = <8>;
+                                       anatop-vol-bit-width = <5>;
+                                       anatop-min-bit-val = <4>;
+                                       anatop-min-voltage = <800000>;
+                                       anatop-max-voltage = <1375000>;
+                               };
+
+                               regulator-3p0 {
+                                       compatible = "fsl,anatop-regulator";
+                                       regulator-name = "vdd3p0";
+                                       regulator-min-microvolt = <2800000>;
+                                       regulator-max-microvolt = <3150000>;
+                                       regulator-always-on;
+                                       anatop-reg-offset = <0x120>;
+                                       anatop-vol-bit-shift = <8>;
+                                       anatop-vol-bit-width = <5>;
+                                       anatop-min-bit-val = <0>;
+                                       anatop-min-voltage = <2625000>;
+                                       anatop-max-voltage = <3400000>;
+                               };
+
+                               regulator-2p5 {
+                                       compatible = "fsl,anatop-regulator";
+                                       regulator-name = "vdd2p5";
+                                       regulator-min-microvolt = <2000000>;
+                                       regulator-max-microvolt = <2750000>;
+                                       regulator-always-on;
+                                       anatop-reg-offset = <0x130>;
+                                       anatop-vol-bit-shift = <8>;
+                                       anatop-vol-bit-width = <5>;
+                                       anatop-min-bit-val = <0>;
+                                       anatop-min-voltage = <2000000>;
+                                       anatop-max-voltage = <2750000>;
+                               };
+
+                               reg_arm: regulator-vddcore {
+                                       compatible = "fsl,anatop-regulator";
+                                       regulator-name = "vddarm";
+                                       regulator-min-microvolt = <725000>;
+                                       regulator-max-microvolt = <1450000>;
+                                       regulator-always-on;
+                                       anatop-reg-offset = <0x140>;
+                                       anatop-vol-bit-shift = <0>;
+                                       anatop-vol-bit-width = <5>;
+                                       anatop-delay-reg-offset = <0x170>;
+                                       anatop-delay-bit-shift = <24>;
+                                       anatop-delay-bit-width = <2>;
+                                       anatop-min-bit-val = <1>;
+                                       anatop-min-voltage = <725000>;
+                                       anatop-max-voltage = <1450000>;
+                               };
+
+                               reg_pu: regulator-vddpu {
+                                       compatible = "fsl,anatop-regulator";
+                                       regulator-name = "vddpu";
+                                       regulator-min-microvolt = <725000>;
+                                       regulator-max-microvolt = <1450000>;
+                                       regulator-enable-ramp-delay = <150>;
+                                       anatop-reg-offset = <0x140>;
+                                       anatop-vol-bit-shift = <9>;
+                                       anatop-vol-bit-width = <5>;
+                                       anatop-delay-reg-offset = <0x170>;
+                                       anatop-delay-bit-shift = <26>;
+                                       anatop-delay-bit-width = <2>;
+                                       anatop-min-bit-val = <1>;
+                                       anatop-min-voltage = <725000>;
+                                       anatop-max-voltage = <1450000>;
+                               };
+
+                               reg_soc: regulator-vddsoc {
+                                       compatible = "fsl,anatop-regulator";
+                                       regulator-name = "vddsoc";
+                                       regulator-min-microvolt = <725000>;
+                                       regulator-max-microvolt = <1450000>;
+                                       regulator-always-on;
+                                       anatop-reg-offset = <0x140>;
+                                       anatop-vol-bit-shift = <18>;
+                                       anatop-vol-bit-width = <5>;
+                                       anatop-delay-reg-offset = <0x170>;
+                                       anatop-delay-bit-shift = <28>;
+                                       anatop-delay-bit-width = <2>;
+                                       anatop-min-bit-val = <1>;
+                                       anatop-min-voltage = <725000>;
+                                       anatop-max-voltage = <1450000>;
+                               };
+                       };
+
+                       tempmon: tempmon {
+                               compatible = "fsl,imx6q-tempmon";
+                               interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+                               fsl,tempmon = <&anatop>;
+                               fsl,tempmon-data = <&ocotp>;
+                               clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+                       };
+
+                       usbphy1: usbphy@020c9000 {
+                               compatible = "fsl,imx6q-usbphy", 
"fsl,imx23-usbphy";
+                               reg = <0x020c9000 0x1000>;
+                               interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+                               fsl,anatop = <&anatop>;
+                       };
+
+                       usbphy2: usbphy@020ca000 {
+                               compatible = "fsl,imx6q-usbphy", 
"fsl,imx23-usbphy";
+                               reg = <0x020ca000 0x1000>;
+                               interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+                               fsl,anatop = <&anatop>;
+                       };
+
+                       snvs: snvs@020cc000 {
+                               compatible = "fsl,sec-v4.0-mon", "syscon", 
"simple-mfd";
+                               reg = <0x020cc000 0x4000>;
+
+                               snvs_rtc: snvs-rtc-lp {
+                                       compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                       regmap = <&snvs>;
+                                       offset = <0x34>;
+                                       interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <0 20 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               snvs_poweroff: snvs-poweroff {
+                                       compatible = "syscon-poweroff";
+                                       regmap = <&snvs>;
+                                       offset = <0x38>;
+                                       mask = <0x60>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       epit1: epit@020d0000 { /* EPIT1 */
+                               reg = <0x020d0000 0x4000>;
+                               interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       epit2: epit@020d4000 { /* EPIT2 */
+                               reg = <0x020d4000 0x4000>;
+                               interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       src: src@020d8000 {
+                               compatible = "fsl,imx6q-src", "fsl,imx51-src";
+                               reg = <0x020d8000 0x4000>;
+                               interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 96 IRQ_TYPE_LEVEL_HIGH>;
+                               #reset-cells = <1>;
+                       };
+
+                       gpc: gpc@020dc000 {
+                               compatible = "fsl,imx6q-gpc";
+                               reg = <0x020dc000 0x4000>;
+                               interrupt-controller;
+                               #interrupt-cells = <3>;
+                               interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-parent = <&intc>;
+                               pu-supply = <&reg_pu>;
+                               clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                        <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                                        <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                        <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                        <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                        <&clks IMX6QDL_CLK_VPU_AXI>;
+                               #power-domain-cells = <1>;
+                       };
+
+                       gpr: iomuxc-gpr@020e0000 {
+                               compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                               reg = <0x020e0000 0x38>;
+                       };
+
+                       iomuxc: iomuxc@020e0000 {
+                               compatible = "fsl,imx6dl-iomuxc", 
"fsl,imx6q-iomuxc";
+                               reg = <0x020e0000 0x4000>;
+                       };
+
+                       ldb: ldb@020e0008 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+                               gpr = <&gpr>;
+                               status = "disabled";
+
+                               lvds-channel@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+                                       status = "disabled";
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               lvds0_mux_0: endpoint {
+                                                       remote-endpoint = 
<&ipu1_di0_lvds0>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               lvds0_mux_1: endpoint {
+                                                       remote-endpoint = 
<&ipu1_di1_lvds0>;
+                                               };
+                                       };
+                               };
+
+                               lvds-channel@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+                                       status = "disabled";
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               lvds1_mux_0: endpoint {
+                                                       remote-endpoint = 
<&ipu1_di0_lvds1>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               lvds1_mux_1: endpoint {
+                                                       remote-endpoint = 
<&ipu1_di1_lvds1>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       dcic1: dcic@020e4000 {
+                               reg = <0x020e4000 0x4000>;
+                               interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       dcic2: dcic@020e8000 {
+                               reg = <0x020e8000 0x4000>;
+                               interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sdma: sdma@020ec000 {
+                               compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+                               reg = <0x020ec000 0x4000>;
+                               interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_SDMA>,
+                                        <&clks IMX6QDL_CLK_SDMA>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = 
"imx/sdma/sdma-imx6q.bin";
+                       };
+               };
+
+               aips-bus@02100000 { /* AIPS2 */
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x02100000 0x100000>;
+                       ranges;
+
+                       crypto: caam@2100000 {
+                               compatible = "fsl,sec-v4.0";
+                               fsl,sec-era = <4>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x2100000 0x10000>;
+                               ranges = <0 0x2100000 0x10000>;
+                               clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+                                        <&clks IMX6QDL_CLK_CAAM_ACLK>,
+                                        <&clks IMX6QDL_CLK_CAAM_IPG>,
+                                        <&clks IMX6QDL_CLK_EIM_SLOW>;
+                               clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+                               sec_jr0: jr0@1000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x1000 0x1000>;
+                                       interrupts = <GIC_SPI 105 
IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr1: jr1@2000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x2000 0x1000>;
+                                       interrupts = <GIC_SPI 106 
IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                       };
+
+                       aipstz@0217c000 { /* AIPSTZ2 */
+                               reg = <0x0217c000 0x4000>;
+                       };
+
+                       usbotg: usb@02184000 {
+                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                               reg = <0x02184000 0x200>;
+                               interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USBOH3>;
+                               fsl,usbphy = <&usbphy1>;
+                               fsl,usbmisc = <&usbmisc 0>;
+                               ahb-burst-config = <0x0>;
+                               tx-burst-size-dword = <0x10>;
+                               rx-burst-size-dword = <0x10>;
+                               status = "disabled";
+                       };
+
+                       usbh1: usb@02184200 {
+                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                               reg = <0x02184200 0x200>;
+                               interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USBOH3>;
+                               fsl,usbphy = <&usbphy2>;
+                               fsl,usbmisc = <&usbmisc 1>;
+                               dr_mode = "host";
+                               ahb-burst-config = <0x0>;
+                               tx-burst-size-dword = <0x10>;
+                               rx-burst-size-dword = <0x10>;
+                               status = "disabled";
+                       };
+
+                       usbh2: usb@02184400 {
+                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                               reg = <0x02184400 0x200>;
+                               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USBOH3>;
+                               fsl,usbmisc = <&usbmisc 2>;
+                               dr_mode = "host";
+                               ahb-burst-config = <0x0>;
+                               tx-burst-size-dword = <0x10>;
+                               rx-burst-size-dword = <0x10>;
+                               status = "disabled";
+                       };
+
+                       usbh3: usb@02184600 {
+                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                               reg = <0x02184600 0x200>;
+                               interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USBOH3>;
+                               fsl,usbmisc = <&usbmisc 3>;
+                               dr_mode = "host";
+                               ahb-burst-config = <0x0>;
+                               tx-burst-size-dword = <0x10>;
+                               rx-burst-size-dword = <0x10>;
+                               status = "disabled";
+                       };
+
+                       usbmisc: usbmisc@02184800 {
+                               #index-cells = <1>;
+                               compatible = "fsl,imx6q-usbmisc";
+                               reg = <0x02184800 0x200>;
+                               clocks = <&clks IMX6QDL_CLK_USBOH3>;
+                       };
+
+                       fec: ethernet@02188000 {
+                               compatible = "fsl,imx6q-fec";
+                               reg = <0x02188000 0x4000>;
+                               interrupts-extended =
+                                       <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
+                                       <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_ENET>,
+                                        <&clks IMX6QDL_CLK_ENET>,
+                                        <&clks IMX6QDL_CLK_ENET_REF>;
+                               clock-names = "ipg", "ahb", "ptp";
+                               status = "disabled";
+                       };
+
+                       mlb@0218c000 {
+                               reg = <0x0218c000 0x4000>;
+                               interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 117 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 126 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       usdhc1: usdhc@02190000 {
+                               compatible = "fsl,imx6q-usdhc";
+                               reg = <0x02190000 0x4000>;
+                               interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USDHC1>,
+                                        <&clks IMX6QDL_CLK_USDHC1>,
+                                        <&clks IMX6QDL_CLK_USDHC1>;
+                               clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       usdhc2: usdhc@02194000 {
+                               compatible = "fsl,imx6q-usdhc";
+                               reg = <0x02194000 0x4000>;
+                               interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USDHC2>,
+                                        <&clks IMX6QDL_CLK_USDHC2>,
+                                        <&clks IMX6QDL_CLK_USDHC2>;
+                               clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       usdhc3: usdhc@02198000 {
+                               compatible = "fsl,imx6q-usdhc";
+                               reg = <0x02198000 0x4000>;
+                               interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USDHC3>,
+                                        <&clks IMX6QDL_CLK_USDHC3>,
+                                        <&clks IMX6QDL_CLK_USDHC3>;
+                               clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       usdhc4: usdhc@0219c000 {
+                               compatible = "fsl,imx6q-usdhc";
+                               reg = <0x0219c000 0x4000>;
+                               interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_USDHC4>,
+                                        <&clks IMX6QDL_CLK_USDHC4>,
+                                        <&clks IMX6QDL_CLK_USDHC4>;
+                               clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       i2c1: i2c@021a0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+                               reg = <0x021a0000 0x4000>;
+                               interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_I2C1>;
+                               status = "disabled";
+                       };
+
+                       i2c2: i2c@021a4000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+                               reg = <0x021a4000 0x4000>;
+                               interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_I2C2>;
+                               status = "disabled";
+                       };
+
+                       i2c3: i2c@021a8000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+                               reg = <0x021a8000 0x4000>;
+                               interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_I2C3>;
+                               status = "disabled";
+                       };
+
+                       romcp@021ac000 {
+                               reg = <0x021ac000 0x4000>;
+                       };
+
+                       mmdc0: mmdc@021b0000 { /* MMDC0 */
+                               compatible = "fsl,imx6q-mmdc";
+                               reg = <0x021b0000 0x4000>;
+                       };
+
+                       mmdc1: mmdc@021b4000 { /* MMDC1 */
+                               reg = <0x021b4000 0x4000>;
+                       };
+
+                       weim: weim@021b8000 {
+                               compatible = "fsl,imx6q-weim";
+                               reg = <0x021b8000 0x4000>;
+                               interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+                       };
+
+                       ocotp: ocotp@021bc000 {
+                               compatible = "fsl,imx6q-ocotp", "syscon";
+                               reg = <0x021bc000 0x4000>;
+                               clocks = <&clks IMX6QDL_CLK_IIM>;
+                       };
+
+                       tzasc@021d0000 { /* TZASC1 */
+                               reg = <0x021d0000 0x4000>;
+                               interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       tzasc@021d4000 { /* TZASC2 */
+                               reg = <0x021d4000 0x4000>;
+                               interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       audmux: audmux@021d8000 {
+                               compatible = "fsl,imx6q-audmux", 
"fsl,imx31-audmux";
+                               reg = <0x021d8000 0x4000>;
+                               status = "disabled";
+                       };
+
+                       mipi_csi: mipi@021dc000 {
+                               reg = <0x021dc000 0x4000>;
+                       };
+
+                       mipi_dsi: mipi@021e0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x021e0000 0x4000>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               mipi_mux_0: endpoint {
+                                                       remote-endpoint = 
<&ipu1_di0_mipi>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mipi_mux_1: endpoint {
+                                                       remote-endpoint = 
<&ipu1_di1_mipi>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       vdoa@021e4000 {
+                               reg = <0x021e4000 0x4000>;
+                               interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       uart2: serial@021e8000 {
+                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                               reg = <0x021e8000 0x4000>;
+                               interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+                                        <&clks IMX6QDL_CLK_UART_SERIAL>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       uart3: serial@021ec000 {
+                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                               reg = <0x021ec000 0x4000>;
+                               interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+                                        <&clks IMX6QDL_CLK_UART_SERIAL>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       uart4: serial@021f0000 {
+                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                               reg = <0x021f0000 0x4000>;
+                               interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+                                        <&clks IMX6QDL_CLK_UART_SERIAL>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       uart5: serial@021f4000 {
+                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                               reg = <0x021f4000 0x4000>;
+                               interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+                                        <&clks IMX6QDL_CLK_UART_SERIAL>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+               };
+
+               ipu1: ipu@02400000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "fsl,imx6q-ipu";
+                       reg = <0x02400000 0x400000>;
+                       interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 5 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6QDL_CLK_IPU1>,
+                                <&clks IMX6QDL_CLK_IPU1_DI0>,
+                                <&clks IMX6QDL_CLK_IPU1_DI1>;
+                       clock-names = "bus", "di0", "di1";
+                       resets = <&src 2>;
+
+                       ipu1_csi0: port@0 {
+                               reg = <0>;
+                       };
+
+                       ipu1_csi1: port@1 {
+                               reg = <1>;
+                       };
+
+                       ipu1_di0: port@2 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <2>;
+
+                               ipu1_di0_disp0: disp0-endpoint {
+                               };
+
+                               ipu1_di0_hdmi: hdmi-endpoint {
+                                       remote-endpoint = <&hdmi_mux_0>;
+                               };
+
+                               ipu1_di0_mipi: mipi-endpoint {
+                                       remote-endpoint = <&mipi_mux_0>;
+                               };
+
+                               ipu1_di0_lvds0: lvds0-endpoint {
+                                       remote-endpoint = <&lvds0_mux_0>;
+                               };
+
+                               ipu1_di0_lvds1: lvds1-endpoint {
+                                       remote-endpoint = <&lvds1_mux_0>;
+                               };
+                       };
+
+                       ipu1_di1: port@3 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <3>;
+
+                               ipu1_di1_disp1: disp1-endpoint {
+                               };
+
+                               ipu1_di1_hdmi: hdmi-endpoint {
+                                       remote-endpoint = <&hdmi_mux_1>;
+                               };
+
+                               ipu1_di1_mipi: mipi-endpoint {
+                                       remote-endpoint = <&mipi_mux_1>;
+                               };
+
+                               ipu1_di1_lvds0: lvds0-endpoint {
+                                       remote-endpoint = <&lvds0_mux_1>;
+                               };
+
+                               ipu1_di1_lvds1: lvds1-endpoint {
+                                       remote-endpoint = <&lvds1_mux_1>;
+                               };
+                       };
+               };
+       };
+};
-- 
2.7.4


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