> -----Original Message----- > From: Atish Patra <atish.pa...@wdc.com> > Sent: Thursday, March 7, 2019 5:20 AM > To: Anup Patel <a...@brainfault.org>; Auer, Lukas > <lukas.a...@aisec.fraunhofer.de> > Cc: sch...@suse.de; paul.walms...@sifive.com; ag...@suse.de; u- > b...@lists.denx.de; bar...@tkos.co.il; daniel.schwierz...@gmail.com; > bmeng...@gmail.com; r...@andestech.com; s...@denx.de; > pal...@sifive.com; Anup Patel <anup.pa...@wdc.com> > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > On 3/6/19 4:32 AM, Anup Patel wrote: > > On Wed, Mar 6, 2019 at 5:45 PM Auer, Lukas > > <lukas.a...@aisec.fraunhofer.de> wrote: > >> > >> On Wed, 2019-03-06 at 13:01 +0100, Andreas Schwab wrote: > >>> On Mär 06 2019, Anup Patel <a...@brainfault.org> wrote: > >>> > >>>> On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <sch...@suse.de> > >>>> wrote: > >>>>> On Mär 06 2019, Anup Patel <anup.pa...@wdc.com> wrote: > >>>>> > >>>>>>> -----Original Message----- > >>>>>>> From: Andreas Schwab <sch...@suse.de> > >>>>>>> Sent: Wednesday, March 6, 2019 4:27 PM > >>>>>>> To: Anup Patel <anup.pa...@wdc.com> > >>>>>>> Cc: Auer, Lukas <lukas.a...@aisec.fraunhofer.de>; > >>>>>>> u-boot@lists.denx.de; paul.walms...@sifive.com; ag...@suse.de; > >>>>>>> a...@brainfault.org; bar...@tkos.co.il; > >>>>>>> daniel.schwierz...@gmail.com; bmeng...@gmail.com; > >>>>>>> r...@andestech.com; s...@denx.de; pal...@sifive.com; Atish Patra > >>>>>>> <atish.pa...@wdc.com> > >>>>>>> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > >>>>>>> > >>>>>>> Apparently sometimes u-boot tries to boot the kernel on heart > >>>>>>> 0 (the E51 > >>>>>>> core), which will then fail to start userspace, since that > >>>>>>> cannot cope with the missing fpu. > >>>>>> > >>>>>> That's not possible > >>>>> > >>>>> Yes, it is. > >>>>> > >>>>> > >>>>> OpenSBI v0.3 (Mar 6 2019 10:55:01) > >>>>> ____ _____ ____ _____ > >>>>> / __ \ / ____| _ \_ _| > >>>>> | | | |_ __ ___ _ __ | (___ | |_) || | > >>>>> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > >>>>> | |__| | |_) | __/ | | |____) | |_) || |_ > >>>>> \____/| .__/ \___|_| |_|_____/|____/_____| > >>>>> | | > >>>>> |_| > >>>>> > >>>>> Platform Name : SiFive Freedom U540 > >>>>> Platform HART Features : RV64ACDFIMSU > >>>>> Platform Max HARTs : 5 > >>>>> Current Hart : 2 > >>>>> Firmware Base : 0x80000000 > >>>>> Firmware Size : 88 KB > >>>>> Runtime SBI Version : 0.1 > >>>>> > >>>>> PMP0: 0x0000000080000000-0x000000008001ffff (A) > >>>>> PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) > >>>>> > >>>>> > >>>>> U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 > >>>>> +0100) > >>>>> > >>>>> CPU: rv64imac > >>>>> Model: sifive,hifive-unleashed-a00 > >>>>> DRAM: 8 GiB > >>>> > >>>> How does this prove that U-Boot is booting on HART 0? > >>> > >>> See the CPU isa. > >>> > >> > >> Interesting.. U-Boot assumes that it can run on any core it is > >> started on. In this case, OpenSBI must have booted its payload on hart 0. > > > > This is certainly not reproducible on cold-boot at my end but this > > does mean OpenSBI has booted HART0 and let it jump to U-Boot. > > > > Now OpenSBI (by default) on SiFive FU540 does not allow HART0 to go > > forward due to lack of S-mode. I think this is definitely the > > warm-boot issue where OpenSBI sees corrupted memory contents. > > > > I am able to test both warm-boot and cold-boot several times(>10) without > any issue with following pending PR in openSBI. > > https://github.com/riscv/opensbi/pull/84
Thanks Atish, your changes have been merged in OpenSBI. > > @Andreas @Anup: Can you please apply the above PR on top of master and > verify at your end as well? > > All the harts booted in Linux every time as well. I tried warm-boot 10 times from U-Boot prompt and I did not see any issue at all. I also tried warm-boot 10 times from Linux prompt and I did not see any Issue at all. In both above cases, it came back to U-Boot prompt after warm-boot. Also, tried cold-boot couple of times. I works perfectly fine as well. Like I mentioned, there is no functional issue with this series. The warm-boot issues were fixed in OpenSBI. @Andreas, please try at your end. Regards, Anup _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot