On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut <[email protected]> wrote: > > On 11/7/19 3:10 AM, Ley Foon Tan wrote: > [...] > > diff --git a/arch/arm/mach-socfpga/misc_arria10.c > > b/arch/arm/mach-socfpga/misc_arria10.c > > index 2e2a40b65d..ff6ab83441 100644 > > --- a/arch/arm/mach-socfpga/misc_arria10.c > > +++ b/arch/arm/mach-socfpga/misc_arria10.c > > @@ -28,9 +28,6 @@ > > #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 > > #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 > > > > -static struct socfpga_system_manager *sysmgr_regs = > > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > - > > /* > > * FPGA programming support for SoC FPGA Arria 10 > > */ > > @@ -81,7 +78,7 @@ void socfpga_init_security_policies(void) > > writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); > > writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); > > > > - writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); > > + writel(0x0007FFFF, socfpga_sysmgr_base + SYSMGR_A10_ECC_INTMASK_SET); > > } > > > > void socfpga_sdram_remap_zero(void) > > @@ -105,8 +102,8 @@ int arch_early_init_r(void) > > #if defined(CONFIG_DISPLAY_CPUINFO) > > int print_cpuinfo(void) > > { > > - const u32 bsel = > > - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); > > + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO); > > const u32 Okay. > > > + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo); > > > > puts("CPU: Altera SoCFPGA Arria 10\n"); > > > > diff --git a/arch/arm/mach-socfpga/misc_gen5.c > > b/arch/arm/mach-socfpga/misc_gen5.c > > index b39a66562d..7735958e9c 100644 > > --- a/arch/arm/mach-socfpga/misc_gen5.c > > +++ b/arch/arm/mach-socfpga/misc_gen5.c > > @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; > > > > static struct pl310_regs *const pl310 = > > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > > -static struct socfpga_system_manager *sysmgr_regs = > > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > static struct nic301_registers *nic301_regs = > > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; > > static struct scu_registers *scu_regs = > > @@ -118,8 +116,8 @@ static int socfpga_fpga_id(const bool print_id) > > #if defined(CONFIG_DISPLAY_CPUINFO) > > int print_cpuinfo(void) > > { > > - const u32 bsel = > > - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); > > + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO); > > + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo); > > Same here , const u32 . Okay. > > > puts("CPU: Altera SoCFPGA Platform\n"); > > socfpga_fpga_id(1); > > [...] > > > diff --git a/arch/arm/mach-socfpga/misc_s10.c > > b/arch/arm/mach-socfpga/misc_s10.c > > index 0a5fab11c0..16fbf71599 100644 > > --- a/arch/arm/mach-socfpga/misc_s10.c > > +++ b/arch/arm/mach-socfpga/misc_s10.c > > @@ -23,9 +23,6 @@ > > > > DECLARE_GLOBAL_DATA_PTR; > > > > -static struct socfpga_system_manager *sysmgr_regs = > > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > - > > /* > > * FPGA programming support for SoC FPGA Stratix 10 > > */ > > @@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const > > char *phymode) > > else > > return -EINVAL; > > > > - clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, > > - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, > > - modereg); > > + clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + > > SYSMGR_S10_EMAC0 + > > Is the typecast needed at all ? > Also, the typecast should probably apply only on socfpga_sysmgr_base, > not the entire expression. You are right, don't need typecase here. Will remove it. > > > + gmac_index), > > + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); > > > > return 0; > > } > > [...]
Regards Ley Foon _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
