Le 05/10/2010 10:33, Heiko Schocher a écrit : > Hello Reinhard, > > Reinhard Meyer wrote: >> I _think_ the linker file needs a .align there: >> >> (.data ends with a non-aligned address!) > > actually trying on the tx25 board, and I see a hang after > the dram output too: > > DRAM: 32 MiB > > I inserted a breakpoint in start.S at clear_bss, never reached... > > Maybe the fixloop > > start.S: > [...] > fixnext: > str r1, [r0] > add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ > cmp r2, r3 > ble fixloop > #endif > #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ > > clear_bss: > > never reaches a end ... but just debugging it ... > > register dump in fixloop: > > TX25>ti;r > Core number : 0 > Core state : debug mode (ARM) > Debug entry cause : Single Step > Current PC : 0x812000d8 > Current CPSR : 0x800000d3 (Supervisor) > GPR00: 81fbe020 81fbe1a0 81224364 812285cc > GPR04: 81ebdf88 81ebdf8c 81fe6ac8 81fbe000 > GPR08: 00000017 00dbe000 812285cc 00000000 > GPR12: 00000000 81ebdf88 812006f4 812000d8 > PC : 812000d8 CPSR: 800000d3 > TX25> > > r2 and r3 are a multiple of 8, so this must end, but never > see it ending ...
Ihe loop exit test is a ble, not a bne, so even if r2 or r3 were not properly aligned, this should still exit eventually. A reason why it would not, though, is if the loop trashes the code in RAM. That can happen if e.g. TEXT_BASE is wrong (my bad). In two hour's time I will build (not test) for tx25 and then do a quick check on the content of .rel.dyn and .dynsym in the resulting u-boot. > bye, > Heiko Amicalement, -- Albert. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
