> -----Original Message-----
> From: Lim, Elly Siew Chin <[email protected]>
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Tan, Ley Foon
> <[email protected]>; See, Chin Liang <[email protected]>;
> Simon Goldschmidt <[email protected]>; Chee, Tien Fong
> <[email protected]>; Westergreen, Dalon
> <[email protected]>; Simon Glass <[email protected]>; Gan,
> Yau Wai <[email protected]>; Lim, Elly Siew Chin
> <[email protected]>
> Subject: [v1 05/17] arm: socfpga: Get clock manager base address for Intel
> N5X device
>
> Add N5X clock manager to socfpga_get_managers_addr function.
>
> Signed-off-by: Siew Chin Lim <[email protected]>
> ---
> arch/arm/mach-socfpga/misc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 64a7c9d652..9305bec38a 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void) #ifdef
> CONFIG_TARGET_SOCFPGA_AGILEX
> ret = socfpga_get_base_addr("intel,agilex-clkmgr",
> &socfpga_clkmgr_base);
> +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> + ret = socfpga_get_base_addr("intel,n5x-clkmgr",
> + &socfpga_clkmgr_base);
> #else
> ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
> #endif
> --
> 2.13.0
Reviewed-by: Ley Foon Tan <[email protected]>
