Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt7629.c | 92 +++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index beba7fc4abc..74510ee36a9 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -29,10 +29,12 @@ #define MCU_BUS_SEL(x) ((x) << 9) enum { + CLK_PAD_CLK40M, CLK_PAD_CLK20M, }; static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, [CLK_PAD_CLK20M] = 20 * MHZ, }; @@ -70,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -79,7 +81,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -101,11 +103,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK40M, 1, 1024), + FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK40M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), @@ -141,7 +143,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), - FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), + FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_PAD_CLK40M, 1, 4), FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), @@ -161,7 +163,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; static const struct mtk_parent axi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -172,17 +174,17 @@ static const struct mtk_parent axi_parents[] = { }; static const struct mtk_parent mem_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_DMPLL), }; static const struct mtk_parent ddrphycfg_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent eth_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -193,22 +195,22 @@ static const struct mtk_parent eth_parents[] = { }; static const struct mtk_parent pwm_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent sgmii_ref_1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SGMIIPLL_D2), }; static const struct mtk_parent nfi_infra_parents[] = { - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), @@ -222,7 +224,7 @@ static const struct mtk_parent nfi_infra_parents[] = { }; static const struct mtk_parent flash_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), TOP_PARENT(CLK_TOP_SYSPLL2_D8), TOP_PARENT(CLK_TOP_SYSPLL3_D4), @@ -233,40 +235,40 @@ static const struct mtk_parent flash_parents[] = { }; static const struct mtk_parent uart_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_parent spi0_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL2_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), }; static const struct mtk_parent spi1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL3_D2), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_UNIVPLL1_D8), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), }; static const struct mtk_parent msdc30_0_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D16), TOP_PARENT(CLK_TOP_UNIV48M), }; static const struct mtk_parent msdc30_1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D16), TOP_PARENT(CLK_TOP_UNIV48M), TOP_PARENT(CLK_TOP_SYSPLL2_D4), @@ -277,7 +279,7 @@ static const struct mtk_parent msdc30_1_parents[] = { }; static const struct mtk_parent ap2wbmcu_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIV48M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), @@ -288,45 +290,45 @@ static const struct mtk_parent ap2wbmcu_parents[] = { }; static const struct mtk_parent audio_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; static const struct mtk_parent aud_intbus_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D4), TOP_PARENT(CLK_TOP_SYSPLL4_D2), TOP_PARENT(CLK_TOP_DMPLL_D4), }; static const struct mtk_parent pmicspi_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_SYSPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D16), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), TOP_PARENT(CLK_TOP_DMPLL_D8), }; static const struct mtk_parent scp_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D8), TOP_PARENT(CLK_TOP_UNIVPLL2_D2), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent atb_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL_D5), }; static const struct mtk_parent hif_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL1_D2), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D4), @@ -336,27 +338,27 @@ static const struct mtk_parent hif_parents[] = { }; static const struct mtk_parent sata_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; static const struct mtk_parent usb20_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL3_D4), TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; static const struct mtk_parent aud1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), }; static const struct mtk_parent irrx_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; static const struct mtk_parent crypto_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL1_D2), TOP_PARENT(CLK_TOP_SYSPLL1_D2), @@ -367,7 +369,7 @@ static const struct mtk_parent crypto_parents[] = { }; static const struct mtk_parent gpt10m_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK40M), TOP_PARENT(CLK_TOP_CLKXTAL_D4), }; @@ -574,7 +576,6 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7629_clk_tree = { - .xtal_rate = 40 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -591,7 +592,6 @@ static const struct mtk_clk_tree mt7629_clk_tree = { }; static const struct mtk_clk_tree mt7629_peri_clk_tree = { - .xtal_rate = 40 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -- 2.43.0
