Replace all uses of CLK_XTAL with CLK_PAD_CLK40M. This will eventually let us remove CLK_PARENT_XTAL completely.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt7981.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 685abd844f2..8c2944b7fb3 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -18,8 +18,16 @@ #define MT7981_CLK_PDN 0x250 #define MT7981_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -609,13 +617,16 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), }; static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CB_M_416M, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -628,6 +639,8 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_66M_MCK, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, -- 2.43.0
