Remove the CLK_PARENT_XTAL flag and related code. These have no more users.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mtk.c | 11 ----------- drivers/clk/mediatek/clk-mtk.h | 9 +++------ 2 files changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 0b6eb0dbc04..3557aeac3d5 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -241,8 +241,6 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, parent_dev = clk->dev; break; - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; case CLK_PARENT_EXT: return mtk_ext_clock_get_rate(priv->tree, parent); default: @@ -352,9 +350,6 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags) case CLK_PARENT_INFRASYS: parent_type_str = "infrasys"; break; - case CLK_PARENT_XTAL: - parent_type_str = "xtal"; - break; case CLK_PARENT_EXT: parent_type_str = "ext"; break; @@ -1104,12 +1099,6 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) parent->driver != DM_DRIVER_GET(mtk_clk_topckgen)) { priv = dev_get_priv(parent); parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - } else if (gate->flags & CLK_PARENT_XTAL) { - return priv->tree->xtal_rate; } else if (gate->flags & CLK_PARENT_EXT) { return mtk_ext_clock_get_rate(priv->tree, gate->parent); } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 682b4303585..b39a62edc43 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -8,7 +8,7 @@ #define __DRV_CLK_MTK_H #include <linux/bitops.h> -#define CLK_XTAL 0 + #define MHZ (1000 * 1000) /* flags in struct mtk_clk_tree */ @@ -27,9 +27,8 @@ #define CLK_PARENT_APMIXED BIT(4) #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_INFRASYS BIT(6) -#define CLK_PARENT_XTAL BIT(7) -#define CLK_PARENT_EXT BIT(8) -#define CLK_PARENT_MASK GENMASK(8, 4) +#define CLK_PARENT_EXT BIT(7) +#define CLK_PARENT_MASK GENMASK(7, 4) #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 @@ -120,7 +119,6 @@ struct mtk_parent { #define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED) #define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) #define INFRA_PARENT(id) PARENT(id, CLK_PARENT_INFRASYS) -#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL) #define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT) #define VOID_PARENT PARENT(-1, 0) @@ -233,7 +231,6 @@ struct mtk_gate { /* struct mtk_clk_tree - clock tree */ struct mtk_clk_tree { - unsigned long xtal_rate; const struct mtk_parent pll_parent; /* External fixed clocks - excluded from mapping. */ const ulong *ext_clk_rates; -- 2.43.0
