The only missing piece to make rk356x platform completely free now is the source of DDR initialization BLOB provided by Rockchip. This series introduces DRAM controller driver that is ought to be run at TPL stage and initialize DRAM without any BLOBs. Having a DRAM driver in TPL can also let us do some VBE related experiments on rk356x platform, as complete TPL can be built from source.
DRAM initialization code was tested on rk3568 with 4GB of LPDDR4 dram, other configurations was not tested as all boards I have are rk3568 with the same memory configurations. DRAM initialization should also work on rk3566, as the only difference between rk3566 and rk3588 is a maximum DDR operating frequency. So, the maximum frequency was limited by last patch to provide compatibility with rk3566. Looks like rk3562 has the same memory controller and slightly upgraded PHY, so the driver code might be partially reused for rk3562 bringup (if it will ever be done). The driver should also be able to initialize DDR4, but this part is untested because of lack of hardware. LPDDR4x support is missing, but could be added with little effort (should work with LPDDR4 timings slightly patched at runtime, bit 16 of pctl's INIT4 register should be cleared). The series enables LPDDR4 DRAM initialization for rk356x-generic board, other supported boards require CONFIG_RAM_ROCKCHIP_LPDDR4 or CONFIG_RAM_ROCKCHIP_DDR4 to be enabled to build properly. A few questions: The driver uses precalculated timings as most other Rockchip DRAM drivers do, however, timings calculator can be embedded directly into the driver at cost of TPL image size (we have 59.5Kb of SRAM, ~48Kb is used for now). This would allow dynamic DDR type detection (the same way as BLOB does). Should we stay with precalculated timings, or embed the calculator? Calculator code (with few missing bits) can be found in ARM Trusted Firmware sources [1]. What is the correct way to choose different maximum frequency for rk3568 and rk3566? One of possible way to implement this is to move frequency configuration to device tree. Should we choose different operating frequencies for different DDR types then? I am not quite sure about sysreset-psci driver related patch. Are there any boards that have PSCI services up and running at TPL or SPL? I am also not quite sure about rockchip_uart driver in TPL. Should we have one? If we should, we also should have a (heavily cutoff) pinctrl driver that will configure pinmux accordingly? Do we want to have DDR3 and LPDDR3 support? Is there any hardware with such configurations? rk3568's DDR controller supports 4 memory ranks, but I've never seen hardware with such configuration either. Should we support this? There is also commented-out SGRF manipulation code in rk3568_dmc_init function. Left that commented-out, as there is no public SGRF-related documentation, and DRAM is initialized well without setting those. Testing on rk3568 and rk3566 with different DDR configurations is greatly appreciated. Thanks. [1] https://github.com/ayufan-rock64/arm-trusted-firmware/blob/f947c7e05a34db0c5b908a5347184fcaa9a32d95/plat/rockchip/rk322xh/drivers/dram/dram_spec_timing.c --- Pavel Golikov (18): clk: rockchip: rk3568: Fix building with OF_PLATDATA enabled clk: rockchip: rk3568: Fix probe with OF_PLATDATA enabled rockchip: rk3568: syscon: Add PMUGRF support for OF_PLATDATA rockchip: rk3568: syscon: Add MSCH, SGRF and DDRGRF support ram: rockchip: Update ddr pctl regs for px30 ram: rockchip: Add rk3568 lpddr4 support ram: rockchip: Add rk3568 ddr4 support ram: rockchip: Add rk3568 ddr loader params ram: rockchip: Add 4 ranks support to controller code for PX30 ram: rockchip: Add missing bits to common code for sdram driver ram: rockchip: Add SDRAM initialization support for rk3568 clk: rockchip: rk3568: Reduce code size for TPL build rockchip: rk356x: Add register spaces to DMC in u-boot.dtsi rockchip: rk356x: Add DMC related syscons to u-boot.dtsi sysreset: psci: Stop building for XPL rockchip: serial: Add driver alias for rk3568 rockchip: rk356x-generic: Initialize SDRAM at TPL stage ram: rockchip: rk3568: Limit maximum DDR frequency to 1056 MHz arch/arm/dts/rk356x-u-boot.dtsi | 30 +- arch/arm/include/asm/arch-rockchip/clock.h | 1 + arch/arm/include/asm/arch-rockchip/sdram_common.h | 13 +- .../include/asm/arch-rockchip/sdram_pctl_px30.h | 26 +- .../include/asm/arch-rockchip/sdram_phy_rk3568.h | 549 +++ .../asm/arch-rockchip/sdram_phy_ron_rtt_rk3568.h | 209 + arch/arm/include/asm/arch-rockchip/sdram_rk3568.h | 197 + arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/rk3568/Kconfig | 16 + arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 43 +- common/spl/Kconfig.tpl | 1 + configs/generic-rk3568_defconfig | 1 + drivers/clk/rockchip/clk_rk3568.c | 26 +- drivers/ram/rockchip/Makefile | 2 +- .../ram/rockchip/sdram-rk3568-ddr4-detect-1056.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-1184.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-1332.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-1560.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-324.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-396.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-528.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-630.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-780.inc | 75 + .../ram/rockchip/sdram-rk3568-ddr4-detect-920.inc | 75 + .../ram/rockchip/sdram-rk3568-loader_params.inc | 109 + .../rockchip/sdram-rk3568-lpddr4-detect-1056.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-1184.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-1332.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-1560.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-324.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-396.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-528.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-630.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-780.inc | 79 + .../rockchip/sdram-rk3568-lpddr4-detect-920.inc | 79 + drivers/ram/rockchip/sdram_pctl_px30.c | 2 +- drivers/ram/rockchip/sdram_rk3568.c | 4384 +++++++++++++++++++- drivers/serial/serial_rockchip.c | 1 + drivers/sysreset/Makefile | 2 +- 39 files changed, 7164 insertions(+), 16 deletions(-) --- base-commit: 215496fec59b3fa09256b4fb62f92af46e2ec7f9 change-id: 20260517-rk3568-raminit-c6f93f937e54 Best regards, -- Pavel Golikov <[email protected]>
