apply_core_errata() currently runs both Cortex A53 and A57 part checks even when no matching erratum is built in. For boards with no ARM core errata, that means two MIDR_EL1 reads and two comparisons on every CPU entry before lowlevel_init().
Only build the dispatch code when one of the supported errata is enabled. When A57 errata are enabled, read MIDR_EL1 once and reuse the extracted part number. Measured on qemu_arm64_defconfig and ls2080aqds_qspi_defconfig: Case before after qemu start.o text bytes 392 336 qemu linked text bytes 1437007 1436963 qemu dispatch instructions 15 1 ls2080 start.o text bytes 600 576 ls2080 dispatch instructions 33 26 A KVM virt microbench using the same dispatch instruction sequences and one million calls gave: Case before ticks/call after ticks/call speedup no errata path 27.09 20.78 1.30x A57 miss path 28.93 26.50 1.09x Signed-off-by: Josh Law <[email protected]> --- arch/arm/cpu/armv8/start.S | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 40c342e97e9..5c847ed0f85 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -209,30 +209,41 @@ master_cpu: /*-----------------------------------------------------------------------*/ +#if defined(CONFIG_ARM_ERRATA_826974) || defined(CONFIG_ARM_ERRATA_828024) || \ + defined(CONFIG_ARM_ERRATA_829520) || defined(CONFIG_ARM_ERRATA_833069) || \ + defined(CONFIG_ARM_ERRATA_833471) +#define ARMV8_CORTEX_A57_ERRATA +#endif + WEAK(apply_core_errata) +#if defined(CONFIG_ARM_ERRATA_855873) || defined(ARMV8_CORTEX_A57_ERRATA) mov x29, lr /* Save LR */ /* For now, we support Cortex-A53, Cortex-A57 specific errata */ + mrs x0, midr_el1 + ubfx x1, x0, #4, #12 /* CPU part number */ - /* Check if we are running on a Cortex-A53 core */ - branch_if_a53_core x0, apply_a53_core_errata +#ifdef CONFIG_ARM_ERRATA_855873 + cmp x1, #0xD03 /* Cortex-A53 MPCore processor */ + b.eq apply_a53_core_errata +#endif - /* Check if we are running on a Cortex-A57 core */ - branch_if_a57_core x0, apply_a57_core_errata +#ifdef ARMV8_CORTEX_A57_ERRATA + cmp x1, #0xD07 /* Cortex-A57 MPCore processor */ + b.eq apply_a57_core_errata +#endif 0: mov lr, x29 /* Restore LR */ +#endif ret -apply_a53_core_errata: - #ifdef CONFIG_ARM_ERRATA_855873 - mrs x0, midr_el1 +apply_a53_core_errata: tst x0, #(0xf << 20) b.ne 0b - mrs x0, midr_el1 - and x0, x0, #0xf - cmp x0, #3 + and x1, x0, #0xf + cmp x1, #3 b.lt 0b mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ @@ -240,9 +251,10 @@ apply_a53_core_errata: orr x0, x0, #1 << 44 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ isb -#endif b 0b +#endif +#ifdef ARMV8_CORTEX_A57_ERRATA apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 @@ -294,6 +306,7 @@ apply_a57_core_errata: isb #endif b 0b +#endif ENDPROC(apply_core_errata) /*-----------------------------------------------------------------------*/ -- 2.47.3
