From: "Thomas Richard (TI)" <[email protected]> Add support for resuming from suspend in board_init_f. The resume state of the SOC is identified and lpm resume sequence is followed accordingly.
First, add the board specific part of the exit retention sequence for k3-ddrss following the DDR resume sequence: - exit DDR from retention - de-assert the DDR_RET pin - restore DDR max frequency - exit DDR from low power Then: - Extract context address from devicetree and send to TIFS. - Power on the rproc cluster. - Replay the certificates attached to saved images of ATF and OPTEE. - Resume sequence for context restore and rproc resume. - Image entry to DM firmware. (All those steps are done in do_resume()) The context address area is firewalled by TIFS to protect it from other hosts. Co-developed-by: Gregory CLEMENT (TI) <[email protected]> Signed-off-by: Gregory CLEMENT (TI) <[email protected]> Signed-off-by: Thomas Richard (TI) <[email protected]> Co-developed-by: Prasanth Babu Mantena <[email protected]> Signed-off-by: Prasanth Babu Mantena <[email protected]> Co-developed-by: Richard Genoud (TI) <[email protected]> Signed-off-by: Richard Genoud (TI) <[email protected]> --- arch/arm/mach-k3/j721e/j721e_init.c | 64 +++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index f9af0288cf66..a1f87e653299 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -20,9 +20,12 @@ #include <mmc.h> #include <remoteproc.h> #include <k3-avs.h> +#include <power/pmic.h> +#include <mach/k3-ddr.h> #include "../sysfw-loader.h" #include "../common.h" +#include "../lpm-common.h" /* NAVSS North Bridge (NB) registers */ #define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 @@ -294,10 +297,55 @@ void do_dt_magic(void) } #endif +#define GPIO_OUT_1 0x3D +#define DDR_RET_VAL BIT(1) +#define DDR_RET_CLK BIT(2) +#define PMIC_NSLEEP_REG 0x86 + +static void __maybe_unused k3_deassert_DDR_RET(void) +{ + struct udevice *pmica; + struct udevice *pmicb; + int regval; + int ret; + + ret = uclass_get_device_by_name(UCLASS_PMIC, + "pmic@48", &pmica); + if (ret) { + printf("Getting PMICA init failed: %d\n", ret); + return; + } + + ret = uclass_get_device_by_name(UCLASS_PMIC, + "pmic@4c", &pmicb); + if (ret) { + printf("Getting PMICB init failed: %d\n", ret); + return; + } + /* Set DDR_RET Signal Low on PMIC B */ + regval = pmic_reg_read(pmicb, GPIO_OUT_1) & ~DDR_RET_VAL; + + pmic_reg_write(pmicb, GPIO_OUT_1, regval); + + /* Now toggle the CLK of the latch for DDR ret */ + pmic_reg_write(pmicb, GPIO_OUT_1, regval | DDR_RET_CLK); + pmic_reg_write(pmicb, GPIO_OUT_1, regval & ~(DDR_RET_CLK)); + pmic_reg_write(pmicb, GPIO_OUT_1, regval | DDR_RET_CLK); + pmic_reg_write(pmicb, GPIO_OUT_1, regval & ~(DDR_RET_CLK)); + + pmic_reg_write(pmica, PMIC_NSLEEP_REG, 0x3); +} + +__weak bool j7xx_board_is_resuming(void) +{ + return false; +} + void board_init_f(ulong dummy) { int ret; #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) + struct k3_ddrss_regs regs; struct udevice *dev; #endif /* @@ -410,6 +458,22 @@ void board_init_f(ulong dummy) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) panic("DRAM init failed: %d\n", ret); + + if (j7xx_board_is_resuming()) { + /* + * The DDR resume sequence is: + * - exit DDR from retention + * - de-assert the DDR_RET pin + * - restore DDR max frequency + * - exit DDR from low power + */ + k3_ddrss_lpddr4_exit_retention(dev, ®s); + k3_deassert_DDR_RET(); + k3_ddrss_lpddr4_change_freq(dev); + k3_ddrss_lpddr4_exit_low_power(dev, ®s); + + do_resume(); + } #endif spl_enable_cache(); -- 2.47.3
