On Mon, Aug 01, 2011 at 12:20:12PM +0000, Simon Guinot wrote:
> Hi Jason,
>
> On Mon, Aug 01, 2011 at 01:04:27AM +0000, Jason Cooper wrote:
> > If CONFIG_DISPLAY_CPUINFO is enabled on kirkwood SoCs, this will print the
> > speeds of the various components.
> >
> > Signed-off-by: Jason Cooper <[email protected]>
> > ---
> > Changes since v1:
> > - optimized macros to remove one-timers
> > - reduced switch/case to if/else since it operates on one bit.
> > - remove RFC
> >
> > arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 41
> > ++++++++++++++++++++++++++++++
> > arch/arm/include/asm/arch-kirkwood/cpu.h | 1 +
> > 2 files changed, 42 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
> > b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
> > index b4a4c04..818c82f 100644
> > --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
> > +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
> > @@ -270,11 +270,28 @@ static void kw_sysrst_check(void)
> > }
> >
> > #if defined(CONFIG_DISPLAY_CPUINFO)
> > +#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >>
> > 21) | \
> > + ((X & 0x18) >> 1))
> > +#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >>
> > 17))
> > +#define MSAR_DDRCLCK_RTIO_MASK (0xf << 5)
> > +
> > +/*
> > + * TCCLK bit:
> > + * 1 = 166 MHz
> > + * 0 = 200 MHz
> > + */
> > +#define MSAR_TCLCK_MASK 0x00200000
> > +#define MV_BOARD_TCLK_166MHZ 166666667
> > +#define MV_BOARD_TCLK_200MHZ 200000000
> > +
> > int print_cpuinfo(void)
> > {
> > char *rev;
> > u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
> > u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
> > + u32 cpu_clk, t_clk, tmp;
> > + u32 sys_clk, l2_clk;
> > + u32 l2_ratio, ddr_ratio;
> >
> > if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
> > printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n",
> > __FUNCTION__, devid);
> > @@ -297,6 +314,30 @@ int print_cpuinfo(void)
> > }
> >
> > printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
> > +
> > + tmp = readl(MPP_SAMPLE_AT_RESET);
> > + cpu_clk = MSAR_CPUCLCK_EXTRACT(tmp);
> > + if (cpu_clk == 0x9)
> > + cpu_clk = 1200;
> > +
>
> I suspect this code to be broken. Here you get a clock selector (which
> is only relevant for 6281 and 6191 SoCs) from the reset at sample
> register.
Ok, I'll filter on devid, then switch/case on it.
> Which clock frequency do you pick if the selector is not 0x9 ?
Good question. This was originally dreamplug specific code I got from
globalscale. I'm cleaning it up as best I can.
> You should probably use a convertion array from selector to CPU
> frequency. Here is a such array valid for 6281 and 6191 SoCs:
>
> u32 kw_6281_cpu_clk[] = { 0, 0, 0, 0, 600000000, 0, 800000000, 1000000000,
> 0, 1200000000, 0, 0, 1500000000, 0, 0, 0 };
Thanks, I'll integrate this with the above approach.
> Note that I don't know if this array is valid for 6282 and 6283 SoCs.
I'll address it as unhandled in the code.
> But for sure, the clock selector for a 6180 SoC is given by differents
> bits in the reset at sample register: [4:2] against [4:3],[22],[1].
> The conversion array is different too...
If you have the values handy, or a pointer to them, I'll add that as
well.
thx,
Jason.
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