MT7622 currently declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation.
Convert MT7622 to use the generic mtk_gate_clk_data infrastructure. The pciesys and ethsys controllers additionally bind a reset controller, so they are grouped in a dedicated driver that shares the generic probe() function, with a single bind() implementation replacing the two duplicated copies. The remaining controllers (sgmiisys, ssusbsys) are handled by a single generic driver. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> --- drivers/clk/mediatek/clk-mt7622.c | 113 +++++++++++++------------------------- 1 file changed, 39 insertions(+), 74 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 76bc31f06d2..d01e2fe53bf 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -707,32 +707,18 @@ static int mt7622_pericfg_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt7622_peri_clk_tree); } -static int mt7622_pciesys_probe(struct udevice *dev) +static int mt7622_clk_gate_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs, - ARRAY_SIZE(pcie_cgs), 0); -} + struct mtk_gate_clk_data *data; -static int mt7622_pciesys_bind(struct udevice *dev) -{ - int ret = 0; + data = (void *)dev_get_driver_data(dev); - if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { - ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); - if (ret) - debug("Warning: failed to bind reset controller\n"); - } - - return ret; + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, + data->gates, data->num_gates, + data->gates[0].id); } -static int mt7622_ethsys_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs, - ARRAY_SIZE(eth_cgs), 0); -} - -static int mt7622_ethsys_bind(struct udevice *dev) +static int mt7622_clk_gate_reset_bind(struct udevice *dev) { int ret = 0; @@ -745,18 +731,6 @@ static int mt7622_ethsys_bind(struct udevice *dev) return ret; } -static int mt7622_sgmiisys_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs, - ARRAY_SIZE(sgmii_cgs), 0); -} - -static int mt7622_ssusbsys_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs, - ARRAY_SIZE(ssusb_cgs), 0); -} - static const struct udevice_id mt7622_apmixed_compat[] = { { .compatible = "mediatek,mt7622-apmixedsys" }, { } @@ -777,18 +751,33 @@ static const struct udevice_id mt7622_pericfg_compat[] = { { } }; -static const struct udevice_id mt7622_pciesys_compat[] = { - { .compatible = "mediatek,mt7622-pciesys", }, - { } -}; +MTK_GATE_CLK_DATA(pcie_cgs); +MTK_GATE_CLK_DATA(eth_cgs); -static const struct udevice_id mt7622_ethsys_compat[] = { - { .compatible = "mediatek,mt7622-ethsys", }, +static const struct udevice_id mt7622_clk_gate_reset_compat[] = { + { + .compatible = "mediatek,mt7622-pciesys", + .data = (ulong)&pcie_cgs_data + }, + { + .compatible = "mediatek,mt7622-ethsys", + .data = (ulong)ð_cgs_data + }, { } }; -static const struct udevice_id mt7622_sgmiisys_compat[] = { - { .compatible = "mediatek,mt7622-sgmiisys", }, +MTK_GATE_CLK_DATA(sgmii_cgs); +MTK_GATE_CLK_DATA(ssusb_cgs); + +static const struct udevice_id mt7622_clk_gate_compat[] = { + { + .compatible = "mediatek,mt7622-sgmiisys", + .data = (ulong)&sgmii_cgs_data + }, + { + .compatible = "mediatek,mt7622-ssusbsys", + .data = (ulong)&ssusb_cgs_data + }, { } }; @@ -797,11 +786,6 @@ static const struct udevice_id mt7622_mcucfg_compat[] = { { } }; -static const struct udevice_id mt7622_ssusbsys_compat[] = { - { .compatible = "mediatek,mt7622-ssusbsys" }, - { } -}; - U_BOOT_DRIVER(mt7622_mcucfg) = { .name = "mt7622-mcucfg", .id = UCLASS_SYSCON, @@ -852,40 +836,21 @@ U_BOOT_DRIVER(mt7622_clk_pericfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mt7622_clk_pciesys) = { - .name = "mt7622-clock-pciesys", - .id = UCLASS_CLK, - .of_match = mt7622_pciesys_compat, - .probe = mt7622_pciesys_probe, - .bind = mt7622_pciesys_bind, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, -}; - -U_BOOT_DRIVER(mt7622_clk_ethsys) = { - .name = "mt7622-clock-ethsys", - .id = UCLASS_CLK, - .of_match = mt7622_ethsys_compat, - .probe = mt7622_ethsys_probe, - .bind = mt7622_ethsys_bind, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, -}; - -U_BOOT_DRIVER(mt7622_clk_sgmiisys) = { - .name = "mt7622-clock-sgmiisys", +U_BOOT_DRIVER(mt7622_clk_gate_reset) = { + .name = "mt7622-gate-clk-reset", .id = UCLASS_CLK, - .of_match = mt7622_sgmiisys_compat, - .probe = mt7622_sgmiisys_probe, + .of_match = mt7622_clk_gate_reset_compat, + .probe = mt7622_clk_gate_probe, + .bind = mt7622_clk_gate_reset_bind, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; -U_BOOT_DRIVER(mt7622_clk_ssusbsys) = { - .name = "mt7622-clock-ssusbsys", +U_BOOT_DRIVER(mt7622_clk_gate) = { + .name = "mt7622-gate-clk", .id = UCLASS_CLK, - .of_match = mt7622_ssusbsys_compat, - .probe = mt7622_ssusbsys_probe, + .of_match = mt7622_clk_gate_compat, + .probe = mt7622_clk_gate_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; -- 2.54.0
