Add clock tree type flags to the mt7988 clock tree structures. These will be used later for parent lookup.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt7988.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 4e19f285da0..309b6e03ceb 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -808,6 +808,7 @@ static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, + .type = MTK_CLK_TREE_APMIXED, }; static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { @@ -822,6 +823,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), .flags = CLK_PARENT_TOPCKGEN, + .type = MTK_CLK_TREE_TOPCKGEN, }; static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { @@ -833,6 +835,12 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), + .type = MTK_CLK_TREE_INFRASYS, +}; + +static const struct mtk_clk_tree mt7988_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct udevice_id mt7988_fixed_pll_compat[] = { @@ -867,6 +875,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = { .name = "mt7988-clock-fixed-pll", .id = UCLASS_CLK, .of_match = mt7988_fixed_pll_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt7988_fixed_pll_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_fixed_pll_ops, @@ -877,6 +886,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .name = "mt7988-clock-topckgen", .id = UCLASS_CLK, .of_match = mt7988_topckgen_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt7988_topckgen_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, @@ -897,6 +907,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .name = "mt7988-clock-infracfg", .id = UCLASS_CLK, .of_match = mt7988_infracfg_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt7988_infracfg_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_infrasys_ops, @@ -924,8 +935,7 @@ static const struct mtk_gate ethdma_mtk_gate[] = { static int mt7988_ethdma_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, - ethdma_mtk_gate, + return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, ethdma_mtk_gate, ARRAY_SIZE(ethdma_mtk_gate), 0); } @@ -983,7 +993,7 @@ static const struct mtk_gate sgmiisys_0_mtk_gate[] = { static int mt7988_sgmiisys_0_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, + return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, sgmiisys_0_mtk_gate, ARRAY_SIZE(sgmiisys_0_mtk_gate), 0); } @@ -1028,7 +1038,7 @@ static const struct mtk_gate sgmiisys_1_mtk_gate[] = { static int mt7988_sgmiisys_1_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, + return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, sgmiisys_1_mtk_gate, ARRAY_SIZE(sgmiisys_1_mtk_gate), 0); } @@ -1075,7 +1085,7 @@ static const struct mtk_gate ethwarp_mtk_gate[] = { static int mt7988_ethwarp_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, + return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, ethwarp_mtk_gate, ARRAY_SIZE(ethwarp_mtk_gate), 0); } -- 2.43.0
