Add clock tree type flags to the mt8183 clock tree structures. These will be used later for parent lookup.
Clock trees had to be split now that each tree has a different type flag. Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt8183.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 7b2d796bc6c..ea98b63d9f5 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -604,20 +604,32 @@ static const struct mtk_composite top_muxes[] = { MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), }; -static const struct mtk_clk_tree mt8183_clk_tree = { +static const struct mtk_clk_tree mt8183_apmixed_clk_tree = { .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), + .type = MTK_CLK_TREE_APMIXED, +}; + +static const struct mtk_clk_tree mt8183_topckgen_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CLK13M, .muxes_offs = CLK_TOP_MUX_AXI, - .plls = apmixed_plls, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .num_plls = ARRAY_SIZE(apmixed_plls), .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), + .type = MTK_CLK_TREE_TOPCKGEN, +}; + +static const struct mtk_clk_tree mt8183_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs infra0_cg_regs = { @@ -782,12 +794,12 @@ static const struct mtk_gate infra_clks[] = { static int mt8183_apmixedsys_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt8183_clk_tree); + return mtk_common_clk_init(dev, &mt8183_apmixed_clk_tree); } static int mt8183_topckgen_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt8183_clk_tree); + return mtk_common_clk_init(dev, &mt8183_topckgen_clk_tree); } static int mt8183_infracfg_probe(struct udevice *dev) @@ -815,6 +827,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = { .name = "mt8183-apmixedsys", .id = UCLASS_CLK, .of_match = mt8183_apmixed_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt8183_apmixedsys_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_apmixedsys_ops, @@ -825,6 +838,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .name = "mt8183-topckgen", .id = UCLASS_CLK, .of_match = mt8183_topckgen_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt8183_topckgen_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, -- 2.43.0
