On 2026-07-21T15:21:05, Aristo Chen <[email protected]> wrote: > arm: dts: k3: phycore: widen SPL overlay load address spacing > > The phyCORE AM62x, AM62Ax and AM64x u-boot FIT images carry four > devicetree overlays (som-no-rtc, som-no-spi, som-no-eth, som-qspi) > that SPL loads simultaneously as loadables of the same configuration. > Their load addresses are spaced only 4 KiB apart, but each packaged > image is larger than that. Measured on a phycore_am62x build, every > overlay is between 6035 and 6163 bytes including the prepended > ti-secure certificate, and the raw dtbo that remains in memory after > the certificate is stripped is still around 4.2 to 4.4 KiB. > > Loading the images back to back therefore overwrites the tail of the > previously loaded overlay, so by the time the board code applies the > overlays from the recorded /fit-images addresses the earlier ones are > already corrupted. > > Space the overlay slots 16 KiB apart so each image has comfortable > headroom. The addresses are only consumed through the /fit-images > records that SPL writes while loading the images, so no other code > needs to change. This also allows the upcoming mkimage load address > overlap check to pass for these boards. > > Signed-off-by: Aristo Chen <[email protected]> > Tested-by: Wadim Egorov <[email protected]> > > arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 6 +++--- > arch/arm/dts/k3-am62a-phycore-som-binman.dtsi | 6 +++--- > arch/arm/dts/k3-am642-phycore-som-binman.dtsi | 6 +++--- > 3 files changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass <[email protected]>
