The ore PLLs are only initialized in SPL on RK3576. Ensure clock driver is always probed after bind for SPL builds to initialize core PLLs and clocks in SPL phase on RK3576.
Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_rk3576.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index 75b705ffba2f..1988f0472dec 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -2526,6 +2526,10 @@ static int rk3576_clk_bind(struct udevice *dev) struct udevice *sys_child; struct sysreset_reg *priv; + /* Ensure clocks are initialized after bind in SPL build */ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + /* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", &sys_child); -- 2.54.0
