Hi Jonas, On 2026-08-04T00:26:39, Jonas Karlman <[email protected]> wrote: > clk: rockchip: rk3568: Always init clocks in SPL build > > The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.
> > Ensure clock driver is always probed after bind for SPL builds to > initialize core PLLs and clocks in SPL phase on RK3568. Just to check: "is initialized to 150 MHz" reads as if this already happens. My understanding is that probe() contains the ACLK_BUS setup, but nothing forces the CRU to be probed in SPL, so it is silently skipped. Please spell that out - something like "the clock driver is currently only probed on demand, so the ACLK_BUS init in probe() is skipped when no SPL consumer references it" - so the motivation matches the speedup Alexey reported on the rk3576 patch. > > Ensure clock driver is always probed after bind for SPL builds to > initialize core PLLs and clocks in SPL phase on RK3568. > > Signed-off-by: Jonas Karlman <[email protected]> > > drivers/clk/rockchip/clk_rk3568.c | 4 ++++ > 1 file changed, 4 insertions(+) > diff --git a/drivers/clk/rockchip/clk_rk3568.c > b/drivers/clk/rockchip/clk_rk3568.c > @@ -2938,6 +2938,10 @@ static int rk3568_clk_bind(struct udevice *dev) > struct udevice *sys_child; > struct sysreset_reg *priv; > > + /* Ensure clocks are initialized after bind in SPL build */ > + if (IS_ENABLED(CONFIG_SPL_BUILD)) > + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); > + Have you considered marking the CRU node bootph-all (or equivalent) in the DT instead? That is the more usual DM way to force a device up early, and it avoids sprinkling a phase check into every SoC driver. If PROBE_AFTER_BIND is genuinely the right hammer here, please add a note in the commit message explaining why. Regards, Simon
