Hi, I didn't know about the submission when I was making this, apologies.
Yes, you're right, it is doing the same thing as your patch. I also wish it could be applied first, then I could put mine on top of it. It seems like a more elegant solution compared to my own. -- Regards, Reza Kurniawan On Tue, Sep 15, 2026 at 4:45 PM Alexey Minnekhanov <[email protected]> wrote: > > On 12.09.2026 10:23, Reza Kurniawan via groups.io wrote: > > Some SoCs such as MSM8917 poll its GDSC power domains by reading GDSCR > > directly, as opposed to GDSCR + CFG_GDSCR_OFFSET. > > Add a poll_gdscr flag to struct qcom_power_map to facilitate those SoCs. > > > > Signed-off-by: Reza Kurniawan <[email protected]> > > Reviewed-by: Balaji Selvanathan <[email protected]> > > --- > > > > (no changes since v1) > > > > drivers/clk/qcom/clock-qcom.c | 24 +++++++++++++----------- > > drivers/clk/qcom/clock-qcom.h | 1 + > > 2 files changed, 14 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c > > index 6b46d9db7..754ff4ff4 100644 > > --- a/drivers/clk/qcom/clock-qcom.c > > +++ b/drivers/clk/qcom/clock-qcom.c > > @@ -505,9 +505,9 @@ U_BOOT_DRIVER(qcom_reset) = { > > static int qcom_power_set(struct power_domain *pwr, bool on) > > { > > struct msm_clk_data *data = (struct msm_clk_data > > *)dev_get_driver_data(pwr->dev); > > - void __iomem *base = dev_get_priv(pwr->dev); > > + void __iomem *base = dev_get_priv(pwr->dev), *poll_addr; > > const struct qcom_power_map *map; > > - u32 value; > > + u32 value, mask; > > int ret; > > > > if (pwr->id >= data->num_power_domains) > > @@ -527,19 +527,21 @@ static int qcom_power_set(struct power_domain *pwr, > > bool on) > > > > writel(value, base + map->reg); > > > > - if (on) > > - ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, > > + poll_addr = base + map->reg; > > + if (map->poll_gdscr) { > > + /* Some SOCs such as MSM8917 poll at GDSCR */ > > + ret = readl_poll_timeout(poll_addr, > > value, > > - (value & GDSC_POWER_UP_COMPLETE) || > > - (value & GDSC_PWR_ON_MASK), > > + (!!(value & GDSC_PWR_ON_MASK) == on), > > GDSC_STATUS_POLL_TIMEOUT_US); > > - > > - else > > - ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, > > + } else { > > + mask = on ? GDSC_POWER_UP_COMPLETE : GDSC_POWER_DOWN_COMPLETE; > > + ret = readl_poll_timeout(poll_addr + CFG_GDSCR_OFFSET, > > value, > > - (value & GDSC_POWER_DOWN_COMPLETE) || > > - !(value & GDSC_PWR_ON_MASK), > > + (value & mask) || > > + !!(value & GDSC_PWR_ON_MASK) == on, > > GDSC_STATUS_POLL_TIMEOUT_US); > > + } > > > > if (ret == -ETIMEDOUT) > > printf("WARNING: GDSC %lu is stuck during power on/off\n", > > diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h > > index 3a4550d85..0b514cc1f 100644 > > --- a/drivers/clk/qcom/clock-qcom.h > > +++ b/drivers/clk/qcom/clock-qcom.h > > @@ -76,6 +76,7 @@ struct qcom_reset_map { > > > > struct qcom_power_map { > > unsigned int reg; > > + bool poll_gdscr; > > }; > > > > struct clk; > > Hi, > > It's doing the same as the patch that was already posted, right? [1] > > Sadly it got no reviews, which kind of demotivates any further > contributions to u-boot/qcom. > > [1] > https://lore.kernel.org/u-boot/[email protected]/ > > -- > Regards, > Alexey Minnekhanov
