The pinctrl controller of SpacemiT K3 SoC changed its register BIT layout definition comparing to old K1 SoC, has different IO power-domain tables, and extend drive strength bits to 4.
First patch fix drive strength configuration for external-voltage IO pins. Please note, this series is composed on top of K1 pinctrl patch which sent to mailing list here [1] Link: https://patch.msgid.link/[email protected] [1] Signed-off-by: Yixun Lan <[email protected]> --- Changes in v2: - rebase on top of k1's pinctrl patch - Link to v1: https://patch.msgid.link/[email protected] --- Yixun Lan (2): pinctrl: spacemit: configure drive strength based on power source pinctrl: spacemit: k3: add K3 pin support drivers/pinctrl/spacemit/Kconfig | 4 +- drivers/pinctrl/spacemit/pinctrl-k1.c | 457 +++++++++++++++++++++++++++++----- 2 files changed, 390 insertions(+), 71 deletions(-) --- base-commit: d412c9b0db20ebf497bb2e97e8a727736a4d35a4 change-id: 20260820-01-k3-pinctrl-support-77eefc901e47 Best regards, -- Yixun Lan <[email protected]>
