Configure GPLL6 through the common FSM-voted PLL helper when SDCC1 selects a GPLL6 clock source. This provides the 192 MHz and 384 MHz eMMC source clocks required by Shikra.
Signed-off-by: Abhilash V <[email protected]> --- drivers/clk/qcom/clock-shikra.c | 61 ++++++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/clock-shikra.c b/drivers/clk/qcom/clock-shikra.c index a563e85cb02..9c803e6c181 100644 --- a/drivers/clk/qcom/clock-shikra.c +++ b/drivers/clk/qcom/clock-shikra.c @@ -20,11 +20,35 @@ #define GCC_USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1a034 #define GCC_USB3_PRIM_PHY_AUX_CLK_CMD_RCGR 0x1a060 +#define SHIKRA_GPLL6_MODE_REG 0x6000 +#define SHIKRA_GPLL6_ENA_VOTE_REG 0x79000 +#define SHIKRA_GPLL6_VOTE_BIT BIT(6) +#define SHIKRA_GPLL6_L_VAL 40 +#define SHIKRA_GPLL6_USER_CTL 0x01200109 +#define SHIKRA_GPLL6_USER_CTL_U 0x00000004 +#define SHIKRA_GPLL6_CONFIG_CTL 0x4001055b + +#define SHIKRA_PLL_MODE_ACTIVE_FLAG BIT(30) +#define SHIKRA_PLL_MODE_BIAS_COUNT GENMASK(19, 14) +#define SHIKRA_PLL_MODE_LOCK_COUNT GENMASK(13, 8) +#define SHIKRA_PLL_MODE_VOTE_FSM_ENA BIT(20) +#define SHIKRA_PLL_MODE_BIAS_COUNT_VAL (0x6 << 14) + +#define SHIKRA_PLL_L_VAL_OFFSET 0x4 +#define SHIKRA_PLL_ALPHA_VAL_OFFSET 0x8 +#define SHIKRA_PLL_ALPHA_VAL_U_OFFSET 0xc +#define SHIKRA_PLL_TEST_CTL_OFFSET 0x10 +#define SHIKRA_PLL_TEST_CTL_U_OFFSET 0x14 +#define SHIKRA_PLL_USER_CTL_OFFSET 0x18 +#define SHIKRA_PLL_USER_CTL_U_OFFSET 0x1c +#define SHIKRA_PLL_CONFIG_CTL_OFFSET 0x20 +#define SHIKRA_PLL_LOCK_TIMEOUT_US 200 + static const struct pll_vote_clk gpll6_vote_clk = { .status = 0x6024, .status_bit = BIT(31), - .ena_vote = 0x79000, - .vote_bit = BIT(6), + .ena_vote = SHIKRA_GPLL6_ENA_VOTE_REG, + .vote_bit = SHIKRA_GPLL6_VOTE_BIT, }; static const struct pll_vote_clk gpll7_vote_clk = { @@ -84,6 +108,29 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +/* GPLL6 configuration required by the SDCC1 clock in SPL. */ +static const struct pll_config gpll6_config = { + .mode_reg = SHIKRA_GPLL6_MODE_REG, + .ena_vote = SHIKRA_GPLL6_ENA_VOTE_REG, + .vote_bit = SHIKRA_GPLL6_VOTE_BIT, + .l_val = SHIKRA_GPLL6_L_VAL, + .alpha_val = 0x00000000, + .alpha_val_u = 0x00000000, + .user_ctl = SHIKRA_GPLL6_USER_CTL, + .user_ctl_u = SHIKRA_GPLL6_USER_CTL_U, + .config_ctl = SHIKRA_GPLL6_CONFIG_CTL, + .test_ctl = 0x00000000, + .test_ctl_u = 0x00000000, + .l_val_offset = SHIKRA_PLL_L_VAL_OFFSET, + .alpha_val_offset = SHIKRA_PLL_ALPHA_VAL_OFFSET, + .alpha_val_u_offset = SHIKRA_PLL_ALPHA_VAL_U_OFFSET, + .test_ctl_offset = SHIKRA_PLL_TEST_CTL_OFFSET, + .test_ctl_u_offset = SHIKRA_PLL_TEST_CTL_U_OFFSET, + .user_ctl_offset = SHIKRA_PLL_USER_CTL_OFFSET, + .user_ctl_u_offset = SHIKRA_PLL_USER_CTL_U_OFFSET, + .config_ctl_offset = SHIKRA_PLL_CONFIG_CTL_OFFSET, +}; + static ulong shikra_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -91,20 +138,16 @@ static ulong shikra_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_QUPV3_WRAP0_S0_CLK: - /* - * ftbl_gcc_qupv3_wrap0_s0_clk_src[]'s last entry is - * GPLL6-sourced; vote defensively even though this port's - * only requested rate (debug_uart_clock, 14745600) resolves - * to the GPLL0-sourced entry. - */ + /* The QUP clock table includes a GPLL6 source. */ clk_enable_gpll0(priv->base, &gpll6_vote_clk); freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, GCC_QUPV3_WRAP0_S0_CLK_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; case GCC_SDCC1_APPS_CLK: - clk_enable_gpll0(priv->base, &gpll6_vote_clk); freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate); + if (freq->src == CFG_CLK_SRC_GPLL6) + clk_configure_enable_pll(priv->base, &gpll6_config); clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CLK_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 8); return freq->freq; -- 2.34.1
