Enable QUP wrapper CORE and CORE_2X clocks whenever its master or slave AHB clock is enabled. The wrapper requires these clocks for serial-engine register access.
Signed-off-by: Abhilash V <[email protected]> --- drivers/clk/qcom/clock-shikra.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/qcom/clock-shikra.c b/drivers/clk/qcom/clock-shikra.c index 9c803e6c181..ab07613aa1e 100644 --- a/drivers/clk/qcom/clock-shikra.c +++ b/drivers/clk/qcom/clock-shikra.c @@ -315,6 +315,18 @@ static int shikra_enable(struct clk *clk) debug("%s: clk %ld: %s\n", __func__, clk->id, shikra_clks[clk->id].name); + switch (clk->id) { + case GCC_QUPV3_WRAP_0_M_AHB_CLK: + case GCC_QUPV3_WRAP_0_S_AHB_CLK: + /* + * The wrapper's core clocks are required along with its AHB + * clocks, but are not listed in the wrapper's clock specifiers. + */ + qcom_gate_clk_en(priv, GCC_QUPV3_WRAP0_CORE_CLK); + qcom_gate_clk_en(priv, GCC_QUPV3_WRAP0_CORE_2X_CLK); + break; + } + return qcom_gate_clk_en(priv, clk->id); } -- 2.34.1
