On Thu, Oct 01, 2026 at 10:47:29PM +0200, Vincent Jardin wrote:
> Enrich README.fsl-hwconfig with this sd1 reconfiguration scenarios.
> Add a reference to the Layerscape README.soc.
>
> Signed-off-by: Vincent Jardin <[email protected]>
>
> ---
>
> Changes in v6:
> - Only 161.1328125 MHz PLLS reference clock is supported,
> from the PLLS input or through SRDS_INTRA_REF_CLK_S1 (Vladimir)
>
> Changes in v5:
> - Reword the grouping sentence, suggested by Vladimir
> - PLLS reference clock as an initial condition
> - Drop the MC bullet, and the list of boards
>
> Changes in v4:
> - was v3 5/5, rewritten using a table
>
> .../cpu/armv8/fsl-layerscape/doc/README.soc | 7 ++
> doc/README.fsl-hwconfig | 64 +++++++++++++++++++
> 2 files changed, 71 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> index f2efd4cc1d7..a641e4978aa 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> @@ -331,6 +331,13 @@ LX2160A SoC has 2 more similar SoC personalities
> 2)LX2080A, few difference w.r.t. LX2160A:
> a) Eight 64-bit ARM v8 Cortex-A72 CPUs
>
> +SerDes 1 lane grouping
> + SRDS_PRTCL_S1 is latched at reset. U-Boot can still configure SD1 before
> + the MC starts:
> + 1x100GE + 4x25G, 2x40GE, 1x40GE + 4x10G or 1x100GE + 4x10G.
> + See 'serdes1' in doc/README.fsl-hwconfig, and the 'lx2160_serdes status'
> + command.
> +
>
> LS1028A
> --------
> diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig
> index e752505da49..91bc39d7238 100644
> --- a/doc/README.fsl-hwconfig
> +++ b/doc/README.fsl-hwconfig
> @@ -44,3 +44,67 @@ usb
> usb1:dr_mode=host;usb2:dr_mode=peripheral'
>
> usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host'
> +
> +serdes1
> + Specific to the LX2160A boards whose reset_phy() calls
> + lx2160a_serdes_apply_hwconfig() before mc_env_boot().
> +
> + SRDS_PRTCL_S1 is latched at reset, but the eight SD1 (SerDes) lanes
> + can still be configured before the DPAA2 management complex (MC) starts.
> + This option alters the Ethernet MAC-to-lane grouping after the fact
> + (RCWSR29 keeps reporting the initial protocol).
> +
> + 'serdes1:2x100g'
> + 2x 100GE (CAUI-4), what protocol 13 builds: nothing to do
> +
> + 'serdes1:100g4x25g'
> + 1x 100GE + 4x 25G
> +
> + 'serdes1:2x40g'
> + 2x 40GE (XLAUI-4)
> +
> + 'serdes1:40g4x10g'
> + 1x 40GE + 4x 10G (XFI)
> +
> + 'serdes1:100g4x10g'
> + 1x 100GE + 4x 10G (XFI)
> +
> + Each mode starts from the one in the 'from' column, which is
> + entered first when SD1 is not in it yet, and so on down to what
> + SRDS_PRTCL_S1 built:
> +
> + mode from SRDS_PRTCL_S1 lanes run on
> + 2x100g - 13 PLLF
> + 100g4x25g 2x100g 13 PLLF
> + 2x40g 2x100g 13 PLLS
2x40g should have the "SRDS_PRTCL_S1" field as "13 or 20" as well, no?
Because protocol 20 is literally 2x40g.
> + 40g4x10g 2x40g 13 or 20 PLLS
> + 100g4x10g 2x100g 13 PLLF and PLLS
> +
> + What each mode makes of the two four-lane ports of protocol 13:
Why "of protocol 13"? You could simply say "Active DPMACs for each mode:"
> +
> + mode dpmac.2 port dpmac.1 port
> + 2x100g 100GE 100GE
> + 100g4x25g 100GE 4x 25G: dpmac.3 to dpmac.6
> + 2x40g 40GE 40GE
> + 40g4x10g 40GE 4x XFI: dpmac.3 to dpmac.6
> + 100g4x10g 100GE 4x XFI: dpmac.3 to dpmac.6
For clarity, I would recommend one more column
mode dpmac.1 dpmac.2 dpmac.3 ... dpmac.6
2x100g 100GE 100GE -
100g4x25g - 100GE 4x 25G
2x40g 40GE 40GE -
40g4x10g - 40GE 4x XFI
100g4x10g - 100GE 4x XFI
Also, I think a clarification is in order, that your SerDes1 protocol
naming convention needs to be read from right to left, compared to the
SRDS_PRTCL_S1 table from the hardware RM.
> +
> + Initial conditions:
> +
> + - PLLS needs a 161.1328125 MHz reference clock, for which 2x40g,
> + 40g4x10g and 100g4x10g program it. It can come from the SD1
> + PLLS reference clock input, or from the PLLF one with
> + SRDS_INTRA_REF_CLK_S1=1. A 156.25 MHz PLLS reference clock is
> + not supported. With protocol 13 PLLS is not in use, so nothing
> + checks that clock before these modes start it.
> + - The MC DPC must set follow_hw_pssr in board_info/serdes, for the
> + MC to read the lanes rather than look at protocol, and the DPL
> + must use the dpmacs of the new grouping.
> +
> + 'lx2160_serdes status 1' shows the resulting lane grouping and
> + protocol converters.
> +
> + Example:
> + setenv hwconfig serdes1:100g4x25g
> + saveenv
> + reset
> --
> 2.43.0
>
