Add GENI I2C0 and I2C1 nodes with 400KHz bus speed.
Signed-off-by: Gurumoorthy Santhakumar
<[email protected]>
---
arch/arm/dts/ipq5424-rdp466-u-boot.dtsi | 65 +++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
index 56677cd6f6d..5c9a7384f04 100644
--- a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
+++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
@@ -38,3 +38,68 @@
status = "okay";
};
+ &qupv3 {
+ i2c0: i2c@1a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x1a88000 0x0 0x4000>;
+ reg-names = "se_phys";
+ assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+ assigned-clock-rates = <64000000>;
+ clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+ clock-names = "se";
+ clock-frequency = <400000>;
+ qcom,geni-se-clk-32mhz;
+ pinctrl-0 = <&i2c0_pinmux>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ i2c1: i2c@1a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x1a8c000 0x0 0x4000>;
+ reg-names = "se_phys";
+ assigned-clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+ assigned-clock-rates = <64000000>;
+ clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+ clock-names = "se";
+ clock-frequency = <400000>;
+ qcom,geni-se-clk-32mhz;
+ pinctrl-0 = <&i2c1_pinmux>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+
+ &tlmm {
+ i2c0_pinmux: i2c0 {
+ i2c0_scl {
+ pins = "gpio14";
+ function = "i2c0_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ i2c0_sda {
+ pins = "gpio15";
+ function = "i2c0_sda";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pinmux: i2c1 {
+ i2c1_scl {
+ pins = "gpio16";
+ function = "i2c1_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ i2c1_sda {
+ pins = "gpio17";
+ function = "i2c1_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
--
2.34.1
