Add clock configuration for GENI I2C and support 32 MHz clock rates.
Signed-off-by: Gurumoorthy Santhakumar
<[email protected]>
---
drivers/clk/qcom/clock-ipq5424.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/clock-ipq5424.c b/drivers/clk/qcom/clock-ipq5424.c
index 40823a30ead..470b7eef41c 100644
--- a/drivers/clk/qcom/clock-ipq5424.c
+++ b/drivers/clk/qcom/clock-ipq5424.c
@@ -19,12 +19,35 @@
#include "clock-qcom.h"
#define GCC_IM_SLEEP_CBCR 0x1834020u
+#define GCC_QUPV3_I2C0_CMD_RCGR 0x02018
+#define GCC_QUPV3_I2C0_DIV_CDIVR 0x02020
+#define GCC_QUPV3_I2C1_CMD_RCGR 0x03018
+#define GCC_QUPV3_I2C1_DIV_CDIVR 0x03020
+
+#define IPQ5424_I2C_RCG_DIV 24
+#define IPQ5424_I2C_CDIV 1
static ulong ipq5424_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
+ case GCC_QUPV3_I2C0_CLK:
+ clk_rcg_set_rate_with_post_div(priv->base,
+ GCC_QUPV3_I2C0_CMD_RCGR,
+ GCC_QUPV3_I2C0_DIV_CDIVR,
+ IPQ5424_I2C_RCG_DIV,
+ IPQ5424_I2C_CDIV,
+ CFG_CLK_SRC_GPLL0);
+ return rate;
+ case GCC_QUPV3_I2C1_CLK:
+ clk_rcg_set_rate_with_post_div(priv->base,
+ GCC_QUPV3_I2C1_CMD_RCGR,
+ GCC_QUPV3_I2C1_DIV_CDIVR,
+ IPQ5424_I2C_RCG_DIV,
+ IPQ5424_I2C_CDIV,
+ CFG_CLK_SRC_GPLL0);
+ return rate;
case GCC_QUPV3_UART1_CLK:
clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg,
0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
@@ -38,6 +61,8 @@ static ulong ipq5424_set_rate(struct clk *clk, ulong rate)
}
static const struct gate_clk ipq5424_clks[] = {
+ GATE_CLK(GCC_QUPV3_I2C0_CLK, 0x02024, BIT(0)),
+ GATE_CLK(GCC_QUPV3_I2C1_CLK, 0x03024, BIT(0)),
GATE_CLK(GCC_QUPV3_UART1_CLK, 0x302c, BIT(0)),
GATE_CLK(GCC_SDCC1_AHB_CLK, 0x3303c, BIT(0)),
GATE_CLK(GCC_SDCC1_APPS_CLK, 0x33004, BIT(1)),
--
2.34.1
