Add a helper for RCG rate configuration using RCGR divider and
post-divider settings.

Unlike clk_rcg_set_rate(), it supports fractional dividers and
post-dividers encoded in RCGR.

Signed-off-by: Gurumoorthy Santhakumar 
<[email protected]>
---
 drivers/clk/qcom/clock-qcom.c | 23 +++++++++++++++++++++++
 drivers/clk/qcom/clock-qcom.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 6b46d9db744..7d9de5d2073 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -193,6 +193,29 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, 
int div,
        clk_bcr_update(base + cmd_rcgr);
 }
 
+/* Set an RCG rate and an optional post-divider.*/
+void clk_rcg_set_rate_with_post_div(phys_addr_t base, u32 cmd_rcgr,
+                                   u32 post_div_reg, u32 div,
+                                   u32 post_div, int source)
+{
+       u32 cfg;
+
+       /* setup src select and divider */
+       cfg = readl(base + cmd_rcgr + RCG_CFG_REG);
+       cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK |
+                CFG_SRC_DIV_MASK);
+       cfg |= source & CFG_CLK_SRC_MASK;
+       cfg |= div & CFG_SRC_DIV_MASK;
+
+       writel(cfg, base + cmd_rcgr + RCG_CFG_REG);
+
+       /*optional post divider*/
+       if (post_div_reg)
+               writel(post_div, base + post_div_reg);
+
+       clk_bcr_update(base + cmd_rcgr);
+}
+
 #define PHY_MUX_MASK           GENMASK(1, 0)
 #define PHY_MUX_PHY_SRC                0
 #define PHY_MUX_REF_SRC                2
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 9899cd28aad..3f45bee6b48 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -115,6 +115,9 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t 
cmd_rcgr,
                          int div, int m, int n, int source, u8 mnd_width);
 void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
                      int source);
+void clk_rcg_set_rate_with_post_div(phys_addr_t base, u32 cmd_rcgr,
+                                   u32 post_div_reg, u32 div,
+                                   u32 post_div, int source);
 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
 int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id);
-- 
2.34.1

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