Add the device tree nodes that the N5X DDR retention restore path depends on. Reintroduce the fs-loader node and the &sdr DDR calibration backup properties (firmware-loader, intel,ddrcal-qspi-offset and intel,ddrcal-ddr-offset) that were dropped during the switch to the upstream Linux DT config. These describe where the backup calibration data is stored and the firmware-loader instance used to read it back in SPL.
Document the intel,sdr-ctl-n5x retention properties in doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt. Use bootph-all in place of the legacy u-boot,dm-pre-reloc so the nodes are bound in the pre-relocation SPL phase on the migrated device tree. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Chen Huei Lok <[email protected]> --- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 13 ++++++++ .../ram/intel,sdr-ctl-n5x.txt | 32 +++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi index 3de75f36cbb..ea95d04d37d 100644 --- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -8,6 +8,12 @@ #include "socfpga_n5x-u-boot.dtsi" /{ + fs_loader0: fs-loader { + bootph-all; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0>; + }; + chosen { u-boot,spl-boot-order = &mmc; }; @@ -36,6 +42,13 @@ }; }; +&sdr { + intel,ddrcal-qspi-offset = "0x7000000"; + intel,ddrcal-ddr-offset = "0x100000"; + firmware-loader = <&fs_loader0>; + bootph-all; +}; + &flash0 { bootph-all; cdns,page-size = <256>; diff --git a/doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt b/doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt new file mode 100644 index 00000000000..23b958a1b06 --- /dev/null +++ b/doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt @@ -0,0 +1,32 @@ +* Intel N5X SDRAM controller + +Required properties: +-------------------- +- compatible: must be "intel,sdr-ctl-n5x" + +Optional properties (DDR retention): +------------------------------------ +- intel,ddrcal-qspi-offset: string, hex byte offset of the calibration + backup in QSPI (e.g. "0x7000000"). Used by SPL to load the backup + via the firmware loader. +- intel,ddrcal-ddr-offset: string, hex address in DRAM where a valid + backup is copied after a successful restore (e.g. "0x100000"). +- firmware-loader: phandle to a "u-boot,fs-loader" node used to read + the QSPI backup. If omitted, the loader under /chosen is used. + +Example: +-------- + + fs_loader0: fs-loader { + bootph-all; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0>; + }; + + sdr { + compatible = "intel,sdr-ctl-n5x"; + intel,ddrcal-qspi-offset = "0x7000000"; + intel,ddrcal-ddr-offset = "0x100000"; + firmware-loader = <&fs_loader0>; + bootph-all; + }; -- 2.43.7
